Datasheet
3
HDSL Framer/Mapper for 1168 kbps Applications — LXP710
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
...........................................................................................15
2.1
Multiplexer (MX)..................................................................................................15
2.2
Demultiplexer (DX)..............................................................................................17
2.3
Microprocessor Interface.....................................................................................18
2.4
E1 Interface.........................................................................................................19
2.5
HDSL Interface....................................................................................................20
Register Definitions
.................................................................................................21
Application information
.........................................................................................62
4.1
Target Applications..............................................................................................62
4.2
ETSI Compliant Operation ..................................................................................62
4.3
User Definable HDSL Overhead Bits..................................................................63
4.4
System Software Guidelines...............................................................................65
4.4.1
Board Initialization..................................................................................66
4.4.2
Loop Activation.......................................................................................66
4.4.3
Normal Operation...................................................................................66
4.4.4
Diagnostic Operation..............................................................................67
4.4.5
External Communication ........................................................................67
Test Specifications
..................................................................................................71
Mechanical Specifications
....................................................................................83
3.0
4.0
5.0
6.0
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
LXP710 Block Diagram.........................................................................................9
LXP710 Pinout Diagram......................................................................................10
MX Process.........................................................................................................16
DX Process .........................................................................................................18
E1 Interface with Loopback Switching.................................................................19
HDSL Interface....................................................................................................20
Two-Loop E1 HDSL System ..............................................................................63
Unframed Data Transport Operation...................................................................64
Point-to-Multipoint E1 HDSL System ..................................................................65
Frame Structure of Two Pair Point-to-Point System ...........................................70
E1 Interface Input Timing....................................................................................72
E1 Interface Output Timing .................................................................................73
HDSL Interface Input Timing...............................................................................73
HDSL Interface Output Timing ............................................................................74
Microprocessor Write Cycle
—
Motorola Mode.....................................................75
Microprocessor Read Cycle
—
Motorola Mode.....................................................76
Microprocessor Write Cycle
—
Intel Mode............................................................77
Microprocessor Read Cycle
—
Intel Mode............................................................78
Peak Output Jitter Performance..........................................................................79