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參數(shù)資料
| 型號(hào)： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 11/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
11
Package Topside Markings
Marking
Definition
Part #
Unique identifier for this product family.
Rev #
Identifies the particular silicon
“
stepping
”
—
refer to the specification update for additional stepping
information.
Lot #
Identifies the batch.
FPO #
Identifies the Finish Process Order.
Table 1. Pin Descriptions
Pin
Symbol
I/O
1
Description
1
VCC1
-
+5 Volt Supply
.
2
E1CLKI
DI
E1 Clock Input
. This input clock samples mux E1 data and frame mark inputs. The
sampling edge of this clock can be inverted by the INVMCK control bit. The nominal
frequency of this clock is 2.048 MHz.
3
GND1
-
Ground
.
4
FT16
-
Factory Test
. This pin should not be connected and is reserved for factory test.
5
E1DATI
DI
E1 Data Input
. This input accepts mux E1 data in serial NRZ format.
6
E1FRMI
DI
E1 Frame Sync Input
. This input identifies the first frame bit position of the mux E1 data.
The signal must be High for one E1CLKI period.
7
RESET
DI
Reset
(Active Low). Resets the internal circuits and control registers to their default state
when driven Low.
8
DS
(
RD
)
DI
Data Strobe or Read Enable
. In Intel mode, enables a read cycle when Low. In Motorola
mode, this signal functions as the data strobe. The LXP710 drives the D<7:0> bus with the
contents of the addressed register when
RD
and
CS
are Low.
9
INT6MS
DO
6ms Interrupt
. Can be enabled to go Low for a Mux EOC/Overhead bits Ready, a Demux
EOC/Overhead bits Ready, or a Triple-Echo Message Compare.
10
INTGEN
DO
General Purpose Interrupt
(Active Low). This output can be enabled to go Low when one
or more of the internal general purpose interrupt conditions have been met.
11
MBSE
DI
Motorola Bus Enable
. When MBSE is High, the LXP710 is configured for Motorola bus
mode. When MBSE is Low, the LXP710 is configured for Intel mode. This enable signal
configures the
WR
input to function as R/
W
and the
RD
signal to function as
DS
.
12
TSTEN
DI
Test Mode Enable
. This input should be tied Low to disable factory test modes.
13
TSTMD1
DI
Test Mode 1
. This input should be tied Low and is reserved for factory test modes.
14
15
16
17
18
19
20
21
D7
D6
D5
D4
D3
D2
D1
D0
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
Microprocessor Data Bus
. This 8-bit, bidirectional, tri-state bus is the general purpose
data path that can transfer data between the LXP710 and the microprocessor.
22
VCC2
-
+5 Volt Supply
.
23
FT1
-
Factory Test
. This pin should not be connected and is reserved for factory test.
24
GND2
-
Ground
.
1. DI = digital input; DO = digital output, DI/O = digital input and output; AI = analog input, AO = analog output.
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