- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369884 > LXP710PE Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 39/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
39
Note:
INT6MS interrupt pin corresponds to the interrupt of Mux and Demux 6MS status bits in the
6MSINTSTAT register and triple-echo EOC status bits in IND_3EOCSTAT register.
Indicator and Triple Echo EOC Interrupt Enable Register
Address: 1F
Abbreviation: IND_3EOCINTEN
Read/Write
Indicator and Triple Echo EOC Interrupt Status Register
When a logic
‘
1
’
is written to these registers, these status bits are cleared unless the associated
overhead bit is still active.
Address: 20
Abbreviation: IND_3EOCINTSTAT
Read/Write
2
L3DX6MS
0
Loop 3 demux 6ms interrupt.
1
L2DX6MS
0
Loop 2 demux 6ms interrupt.
0
L1DX6MS
0
Loop 1 demux 6ms interrupt.
Table 32. 6ms Interrupt Status Register (Continued)
Bit
Name
Default
Description
Table 33. Indicator Bits & Triple Echo EOC Enable Register
Bit
Name
Default
Description
<7:6>
n/a
0
Not used; Always read zero.
<5:3>
EIL<3:1>INDCR
0
Enable interrupt on loop <3:1> ready to receive indicator bit.
<2:0>
EIL<3:1>CMP
0
Enable Interrupt on Loop <3:1> EOC Triple-Echo Message Compare. When
High, in addition to enabling the Triple-Echo Message interrupt, the integrated
EOC message (which is updated only when a Triple_Echo message is valid) is
output. When Low, the non-integrated EOC message (updated every 6 ms) is
sent to the receive EOC message register on each loop.
Table 34. Indicator Bits & Triple EOC Status Register
Bit
Name
Default
Description
<7:6>
n/a
0
Not used; Always read zero.
<5:3>
L<3:1>INDCR
0
Loop <3:1> Ready to Receive Indicator. This status bit is active to indicate to
the distant HDSL transceiver that it is ready to receive data.
<2:0>
L<3:1>EOCCMP
0
Loop <3:1> EOC Triple-Echo Message Compare Detected. This status bit is
active only when a new message has been received three consecutive
times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXP730LE | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| LXT1000 | LAN TRANSCEIVER|SINGLE|HYBRID|BGA|492PIN|PLASTIC |
| LXT19908 | Amplifier. Other |
| LXT300JE | PCM Transceiver |
| LXT300NE | PCM Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXP730 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Multi-Rate DSL Framer |
| LXP730LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FRAMER/FORMATTER|CMOS|QFP|64PIN|PLASTIC |
| LXP80 | 制造商:Johnson Components 功能描述: |
| LXPB2SA-50SB-Q | 制造商:SMC Corporation of America 功能描述:Actuator, electric, ball bushing |
| LXPH0000 | 制造商:Red Lion Controls 功能描述:ANNUNCIATOR LABELS, 1 LPAX LABEL: PH 制造商:Red Lion Controls 功能描述:1 LPAX LABEL PH |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。