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參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 14/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
14
Datasheet
72
ICLK3
DI
Loop 3 Transceiver Interface Clock
. This clock input synchronizes the transfer of HDSL
data and frame mark to/from the Loop 3 transceiver. This clock samples the LP3DTI and
RFP3
inputs on rising edge, and outputs the LP3DTO and
TFP3
outputs on the falling edge.
The nominal frequency of this clock signal is 1168 kHz.
73
GND6
-
Ground
.
74
FT11
-
Factory Test
. This pin should not be connected and is reserved for factory test.
75
FT12
-
Factory Test
. This pin should not be connected and is reserved for factory test.
76
FT13
-
Factory Test
. This pin should not be connected and is reserved for factory test.
77
BPVI
DI
BPV Indicator Input
. This pin provides hardware access to the mux HDSL BPV overhead
bit on each loop. An active High pulse on this pin activates the BPV indicator bit on each
loop in the next frame. This signal is ORed with separate software control bits for each
loop that can also activate the BPV bits.
78
LOSDI
DI
Loss of E1 Signal
. This pin provides hardware access to the mux HDSL LOSD overhead
bit on each loop. An active High pulse on this pin activates the LOSD indicator bit on all
loops in the next frame. This signal is ORed with separate software control bits for each
loop that can also activate the LOSD bits.
79
FRCMXAIS
DI
Force Mux AIS
. When enabled by the EXTMXAIS control bit, a High on this bit forces the
mux E1 to insert AIS.
80
E1FRMO
DO
E1 Frame Sync Output
. This output identifies the first frame bit position of the demux E1
data. The signal must be High for one E1CLKO period. The nominal frequency of this
signal is 8 kHz.
81
E1DATO
DO
E1 Data Output
. This output signal provides the data to the external E1 framer.
82
FT14
-
Factory Test
. This pin should not be connected and is reserved for factory test.
83
E1CLKO
DO
E1 Clock Output
. This output is used to synchronize the transfer of E1 frame mark and
data. The output edge of this clock can be inverted by the INVDXCK control bit. The
nominal frequency of this clock is 2.048 MHz.
84
FT15
-
Factory Test
. This pin should not be connected and is reserved for factory test.
Table 1. Pin Descriptions (Continued)
Pin
Symbol
I/O
1
Description
1. DI = digital input; DO = digital output, DI/O = digital input and output; AI = analog input, AO = analog output.
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