HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
37
General Interrupt Enable Register
Address: 1B
Abbreviation: GENINTEN
Read/Write
General Interrupt Vector Status
All of the HDSL overhead status bits in this register are latched active High when detected, and
remain High until a write is done by the microprocessor. When a logic
‘
1
’
is written to these
registers, these status bits are cleared unless the associated overhead bit is still active.
Address: 1C
Abbreviation: GENINTSTAT
Read/Write
2
LPREV[2]
0
000: Directs Loop 1 data to Loop 1 buffer and Loop 2 data to Loop 2 buffer.
001: Directs Loop 1 data to Loop 2 buffer and Loop 2 data to Loop 1 buffer.
010: Directs Loop 1 data to Loop 2 buffer and Loop 2 data to Loop 3 buffer.
011: Directs Loop 1 data to Loop 3 buffer and Loop 2 data to Loop 2 buffer.
100: Directs Loop 1 data to Loop 3 buffer and Loop 2 data to Loop 1 buffer.
101: Directs Loop 1 data to Loop 1 buffer and Loop 2 data to Loop 3 buffer.
1
LPREV[1]
0
0
LPREV[0]
0
Table 28. Loop Reversal Status Register (Continued)
Bit
Name
Default
Description
Table 29. General Interrupt Enable Register
Bit
Name
Default
Description
7
n/a
0
Not used; Always read Low.
6
EIPATLOS
0
Enable interrupt on pattern sync loss.
5
EIECOVR
0
Enable Interrupt on pattern error counter overflow.
4
EILOSD
0
Enable interrupt on demux loop 1 or loop 2 or loop 3 LOSD.
3
EIPS
0
Enable interrupt on demux loop power status indication.
2
EIL3INDC_R
0
Enable interrupt on demux loop 3 indc/indr bit active.
1
EIL2INDC_R
0
Enable interrupt on demux loop 2 indc/indr bit active.
0
EIL1INDC_R
0
Enable interrupt on demux loop 1 indc/indr bit active.
Table 30. General Interrupt Status Register
Bit
Name
Default
Description
7
n/a
0
Not used; Always read Low.
6
IVPATLOS
0
Pattern sync loss.
5
IVECOVR
0
Pattern error counter overflow.
4
IVLOSD
0
Demux loop 1 or loop 2 or loop 3 LOSD.