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參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 19/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
19
In the Motorola Mode (MBSE pin set High), the data bus D<0:7>, address bus A<0:6>, CS, DS
and R/W are used to read or write to the LXP710
’
s internal registers.
In the Intel Mode (MBSE pin set Low), the data bus D<0:7>, address bus A<0:6>, CS, RD and WR
are used to read or write to the LXP710
’
s internal registers. The board design must include a latch,
using ALE, for the address from the Intel multiplexed AD bus. This latch could be shared with the
data pumps and other devices on board that have non-multiplexed address pins.
To optimize code execution, Two external interrupt pins, INTGEN and INT6MS, are provided. The
INTGEN pin is for general purpose interrupts as listed in the GENINTEN and GENINTSTAT
registers in
Table 29
and
Table 30
. The INDCR bits in the IND_3EOCINTEN and
IND_3EOCINTSTAT registers in
Table 33
and
Table 34
are also tied to the INTGEN pin.
The INT6MS pin is for the 6 ms timing related functions such as when the MX eoc and Z-bits are
ready to be loaded to transmit and when the DX eoc and Z-bits have been received. Additionally
the EOC Triple-Echo Message Compare Detected bits in the IND_3EOCINTEN and
IND_3EOCINTSTAT registers (
Table 33
and
Table 34
) are also tied to the INT6MS pin. This
feature reduces software processing needed to detect that a message has been received three times.
2.4
E1 Interface
The E1 interface connects to an E1 framer device. As shown in
Figure 5
, the incoming E1 data is
routed to the MX and is controlled by signals from the E1 framer. The E1 interface takes E1 data
from the DX and provides control signals for the E1 framer. Two loopbacks are available. The first
loopback is for E1 input data to E1 output data. The other is the loopback for the internal DX E1
payload back to the MX block. As shown in the diagram, the two loopbacks are tied together. The
loopback is achieved by setting the E1LB bit in the DXE1CTL register as described in
Table 4
.
Figure 5. E1 Interface with Loopback Switching
MX_E1_CK
MX_E1_FM
MX_E1_DT
DX_E1_DT
DX_E1_FM
DX_E1_CK
E1CLKI
E1FRMI
E1DATI
E1DAT0
E1FRM0
E1CLK0
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