HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
25
NOTE
: Usage of NMCKEN and NMFMEN are:
Operation NMCKEN NMFMEN
Framed service
0
0
Unframed service
0
1
E1 loopback
1
1
E1 loss of signal (LOS) 1
1
(where E1 framer doesn
’
t provide clock in LOS)
Demux E1 Control Register
Address: 01
Abbreviation: DXE1CTL
Read/Write
Table 4. Demux E1 Control Register
Bit
Name
Default
Description
7
INVDXCK
0
Invert Demux E1 Output Clock. When High, the demux E1 data and frame mark
signals are updated on the falling edge of E1CLKO. When this bit is Low, the data
and frame mark are updated on the rising edge.
6
E1LB
0
E1 Loopback. When High, both directions of the E1 NRZ clock, data, and frame mark
are looped back. When Low, normal operation is enabled.
5
TMGSRC1
0
Demux E1 Timing Source Select. These two bits can select the ADPLL output or
nominal clock as E1CLK0.
00: dependent on the status of input pins LOSWx and software setting in LPCTL
register. The loop with first inactive LOSW status will be selected. If all LOSWx are
active, force to nominal clock.
01: force to loop 1
10: force to loop 2
11: force to loop 3
4
TMGSRC0
0
3
DXAIS3
0
Demux Loop 3 AIS Enable. When High, the demux Loop 3 payload is forced to all
ones. When Low, normal operation is enabled.
2
DXAIS2
0
Demux Loop 2 AIS Enable. When High, the demux Loop 2 payload is forced to all
ones. When Low, normal operation is enabled.
1
DXAIS1
0
Demux Loop 1 AIS Enable. When High, the demux Loop 1 payload is forced to all
ones. When Low, normal operation is enabled.
0
EXTDAIS
1
External Demux AIS Enable. When High, the LOSW1 input pin is enabled to force the
demux Loop 1 payload to all ones, LOSW2 input pin is enabled to force the demux
Loop 2 payload to all ones, and LOSW3 input pin is enabled to force the demux Loop
3 payload to all ones. When EXTDAIS is Low, external demux AIS insertion is
disabled.