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參數(shù)資料
| 型號(hào)： | LXP710PE |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 35/84頁(yè) |
| 文件大小： | 1108K |
| 代理商： | LXP710PE |
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HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
35
Test Pattern Error Counter Status Register
All of the HDSL overhead status bits in this register are latched active High when detected, and
remain High until a write is done by the microprocessor.
Address: 16
Abbreviation: PATSTAT
Read/Write
Demux Power Status Register
Address: 17
Abbreviation: DXPSSTAT
Read/Write
All of the HDSL overhead status bits in this register are latched active High when detected, and
remain High until a write is done by the microprocessor.
Note:
Although the HDSL overhead indicator bits are active Low on the HDSL data stream, all status bits
in this register are active High, i.e., the status bits are inverted from what was received on the loop.
Demux HDSL Repeater Present Status Register
Address: 18
Abbreviation: DXHRPSTAT
Table 24. Test Pattern Error Counter Status Register
Bit
Name
Default
Description
<7:6>
n/a
0
Not used; Always read Low.
<5:3>
OVERFLOW<3:1>
0
Loop <3:1> Test Pattern Error Counter Status. When High, Pattern
Error Counter has overflowed.
<2:0>
PATLOS<3:1>
0
Loop <3:1> Sync Pattern Detector Status. When High, Pattern Sync is
lost.
Table 25. Demux Power Status Register
Bit
Name
Default
Description
<7:6>
n/a
0
Not used; Always read Low.
5
DL3PS1
0
Demux Loop3 power status bit #1.
4
DL3PS2
0
Demux Loop3 power status bit #2.
3
DL2PS1
0
Demux Loop2 power status bit #1.
2
DL2PS2
0
Demux Loop2 power status bit #2.
1
DL1PS1
0
Demux Loop 1 power status bit #1.
0
DL1PS2
0
Demux Loop 1 power status bit #2.
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