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參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 28/84頁 |
| 文件大小： | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
28
Datasheet
HDSL Loop 3 Overhead Control Register
Address: 05
Abbreviation: L3OHCTL
Read/Write
Note:
Although the HDSL overhead indicator bits are active Low on the HDSL data stream, all control
bits in this register are active High, i.e., the overhead control bits are inverted before they are
transmitted on the loop.
Time Slot Grouping Table Control Register
Address: 06
Abbreviation: TSCTL
Read/Write
Table 8. HDSL Loop 3 Overhead Control Register
Bit
Name
Default
Description
7
n/a
0
Not used; Always read Low.
6
L3FEBE
0
Mux Loop 3 FEBE Inject (Single-bit). A Low-to-High transition on this bit causes the
mux Loop 3 FEVE overhead bit to be activated for one frame. After the FEBE bit has
been inserted, this control bit is automatically cleared. The FEBE bit is also activated
each time a demux CRC error is detected (on either loop).
5
L3BPV
0
Mux Loop 3 BPV Error Inject (Single-bit). A Low-to-High transition on this bit causes
the mux Loop 3 BPV overhead bit to be activated for one frame. After the BPV bit
has been transmitted, this control bit is automatically cleared. The BPV indicator can
also be activated by the microprocessor.
4
L3CRCE
0
Mux Loop 3 CRC Error Inject (Continuous). When High, a continuous error is
injected in the mux Loop 1 CRC code until this bit is cleared by the microprocessor.
3
L3LOSD
0
Mux Loop 3 LOSD Alarm Activate. When High, the mux Loop 3 LOSD alarm
overhead bit is activated until this bit is reset by the microprocessor. When Low, the
LOSD alarm is sent if the LOSD input pin is active.
2
L3HRP
0
Mux Loop 3 HDSL Repeater Present Control. When High, the mux Loop 3 HRP
overhead bit is activated until this bit is reset by the microprocessor.
1
L3PS1
0
Mux Loop 3 Power Status Bit #1 Control. When High, the mux Loop 3 PS1 overhead
bit is activated until this bit is reset by the microprocessor.
0
L3PS2
0
Mux Loop 3 Power Status Bit #2 Control. When High, the mux Loop 3 PS2 overhead
bit is activated until this bit is reset by the microprocessor.
Table 9. Time Slot Grouping Table Control Register
Bit
Name
Default
Description
7,6
n/a
0
Not used; Always read Low.
5
LPREN3
0
Loop Reversal Detection Enable. When High, enables loop 3 ID detection operation.
4
LPREN2
0
Loop Reversal Detection Enable. When High, enables loop 2 ID detection operation.
3
LPREN1
0
Loop Reversal Detection Enable. When High, enables loop 1 ID detection operation.
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