參數(shù)資料
型號(hào): LXP710PE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 31/84頁
文件大?。?/td> 1108K
代理商: LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
LXP710
Datasheet
31
Address: 0C
Abbreviation: L2TSCTL2
Read/Write
Address: 0D
Abbreviation: L2TSCTL3
Read/Write
Table 14. Loop 2 Time Slot Control Byte 1
Bit
Name
Default
Description
7
TSG0
1
Loop 2 Time Slot Grouping (Byte 1). Each bit that is set Low blocks transmission of
the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
6
TSG1
0
5
TSG2
1
4
TSG3
0
3
TSG4
1
2
TSG5
0
1
TSG6
1
0
TSG7
0
Table 15. Loop 2 Time Slot Control Byte 2
Bit
Name
Default
Description
7
TSG8
1
Loop 2 Time Slot Grouping (Byte 2). Each bit that is set Low blocks transmission of
the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
6
TSG9
0
5
TSG10
1
4
TSG11
0
3
TSG12
1
2
TSG13
0
1
TSG14
1
0
TSG15
0
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