參數(shù)資料
型號(hào)： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 6/84頁(yè)
文件大?。?/td> 1108K
代理商： LXP710PE
LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
6
Datasheet
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Mux Loop 3 Z Bits (MSB)....................................................................................55
Mux Loop 3 EOC Message (High byte) ..............................................................55
Mux Loop 3 EOC Message (Low byte)...............................................................55
Mux Loop 3 UIB Bits ...........................................................................................56
Demux Loop 3 Z Bits (LSB) ................................................................................56
Demux Loop 3 Z Bits...........................................................................................56
Demux Loop 3 Z Bits...........................................................................................56
Demux Loop 3 Z Bits...........................................................................................57
Demux Loop 3 Z Bits...........................................................................................57
Demux Loop 3 Z Bits...........................................................................................57
Demux Loop 3 EOC Message (High byte)..........................................................57
Demux Loop 3 EOC Message (Low byte)...........................................................58
Demux Loop 3 UIB Bits.......................................................................................58
Demux Loop 3 CRC Error Count ........................................................................58
Demux Loop 3 FEBE Error Count.......................................................................59
Demux Loop 3 BPV Error Count.........................................................................59
Loop 3 QRSS Test Pattern Error Counter (High byte)........................................59
Loop 3 QRSS Test Pattern Error Counter (Low byte).........................................59
Loop 3 Mux Restart Counter..............................................................................60
HFMA Version Number.......................................................................................60
Microprocessor Mode Testing Register for Mux .................................................60
Microprocessor Mode Testing Register for Demux.............................................61
HDSL Frame Structure for Two Pair Point-to-Point System ...............................68
Absolute Maximum Ratings ................................................................................71
Recommended Operating Conditions.................................................................71
DC Electrical Characteristics..............................................................................71
E1 Interface Input Timing Specifications (
Figure 11
)..........................................71
E1 Interface Output Timing Specifications (
Figure 12
) .......................................72
HDSL Interface Input Timing Specifications (
Figure 13
).....................................73
HDSL Interface Output Timing Specifications (
Figure 14
) ..................................73
Microprocessor Write Cycle Specifications
—
Motorola Mode (
Table 15
) ............74
Microprocessor Read Cycle Specifications
—
Motorola Mode (
Figure 16
)...........75
Microprocessor Write Cycle Specifications
—
Intel Mode (
Figure 17
)..................76
Microprocessor Read Cycle Specifications
—
Intel Mode (
Figure 18
)..................77
ETSI Maximum Wander Values..........................................................................80
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