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參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 26/84頁 |
| 文件大小： | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
26
Datasheet
HDSL Loop Control Register
Address: 02
Abbreviation: LPCTL
Read/Write
HDSL Loop 1 Overhead Control Register
Address: 03
Abbreviation: L1OHCTL
Read/Write
Table 5. HDSL Loop Control Register
Bit
Name
Default
Description
7
n/a
0
Not used; Always read Low.
6
HDSLLB
0
HDSL Loopback Enable. When High, both directions of the Loop 1, Loop 2 and Loop
3 frame mark and data signals are looped back. When Low, all HDSL loopbacks are
disabled.
5
LOSW3C1
0
LOSW3 S/W Control
Normal Operation: 0x
Force to Active: 10
Force to Inactive: 11
4
LOSW3C0
0
3
LOSW2C1
0
LOSW2 S/W Control
Normal Operation: 0x
Force to Active: 10
Force to Inactive: 11
2
LOSW2C0
0
1
LOSW1C1
0
LOSW1 S/W Control
Normal Operation: 0x
Force to Active: 10
Force to Inactive: 11
0
LOSW1C0
0
Table 6. HDSL Loop 1 Overhead Control Register
Bit
Name
Default
Description
7
n/a
0
Not used; Always read Low.
6
L1FEBE
0
Mux Loop 1 FEBE Inject (Single-bit). A Low-to-High transition on this bit causes the
mux Loop 1 FEBE overhead bit to be activated for one frame. After the FEBE bit has
been inserted, this control bit is automatically cleared. The FEBE bit is also activated
each time a demux CRC error is detected (on either loop).
5
L1BPV
0
Mux Loop 1 BPV Error Inject (Single-bit). A Low-to-High transition on this bit causes
the mux Loop 1 BPV overhead bit to be activated for one frame. After the BPV bit has
been transmitted, this control bit is automatically cleared. The mux BPV indicator bit
can also be activated by the BPV input pin.
4
L1CRCE
0
Mux Loop 1 CRC Error Inject (Continuous). When High, a continuous error is injected
in the mux Loop 1 CRC code until this bit is cleared by the microprocessor.
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