- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369884 > LXP710PE Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 13/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
13
51
FT5
-
Factory Test
. This pin should not be connected and is reserved for factory test.
52
FT6
-
Factory Test
. This pin should not be connected and is reserved for factory test.
53
FT7
-
Factory Test
. This pin should not be connected and is reserved for factory test.
54
LP2DTO
DO
Loop 2 Data Output
. This pin outputs mux data, which is updated on falling edge of
ICLK2, to the Loop 2 transceiver. The nominal bit rate of this signal is 1168 kbps.
55
TFP2
DO
Loop 2 Transmit Frame Pulse
(Active Low). A Low level on this signal indicates the last
bit position of each mux HDSL frame for Loop 2. This position of this pulse is at bit 7006
when no stuffing is added, or bit 7010 when stuffing is added. This pulse nominally occurs
every 6 milliseconds ± 1/584 milliseconds.
56
LOSW2
DI
Loop 2 Loss of Sync Word Status
. This pin inputs the LOSW status from the Loop 2
transceiver. This pin provides hardware override for the demux TMGSRC control bits,
disables Loop 2 error counters, and can demux E1 Partial-AIS. It has an internal pull up
resistor.
57
LP2DTI
DI
Loop 2 Data In
. This signal inputs demux data, which is sampled on rising edge of ICLK1,
from the Loop 2 transceiver. The nominal bit rate of this signal is 1168 kbps.
58
RFP2
DI
Loop 2 Receive Frame Pulse
(Active Low). A Low level on this signal indicates the last bit
position of each demux HDSL frame for Loop 2. The position of this pulse is at bit 7006
when no stuffing is added, or bit 7010 when stuffing is added. This pulse nominally occurs
every 6 milliseconds ± 1/584 milliseconds.
59
FT8
-
Factory Test
. This pin should not be connected and is reserved for factory test.
60
ICLK2
DI
Loop 2 Transceiver Interface Clock
. This clock input synchronizes the transfer of HDSL
data and frame mark to/from the Loop 2 transceiver. This clock samples the LP2DTI and
RFP2
inputs on rising edge, and outputs the LP2DTO and
TFP2
outputs on the falling edge.
The nominal frequency of this clock signal is 1168 kHz.
61
REFCLK
DI
Reference Clock.
Provides 18.688 MHz reference clock for HDSL Loopback test.
62
VCC5
-
+5 Volt Supply
.
63
FT10
-
Factory Test
. This pin should not be connected and is reserved for factory test.
64
GND5
-
Ground
.
65
LTU
DI
LTU Mode Enable
. When this input is High, the LTU mode is selected otherwise, the NTU
mode is selected.
66
LP3DTO
DO
Loop 3 Data Output
. This pin outputs mux data, which is updated on falling edge of
ICLK3, to the Loop 3 transceiver. The nominal bit rate of this signal is 1168 kbps.
67
TFP3
DO
Loop 3 Transmit Frame Pulse
(Active Low). A Low level on this signal indicates the last
bit position of each mux HDSL frame for Loop 3. This position of this pulse is at bit 7006
when no stuffing is added, or bit 7010 when stuffing is added. This pulse nominally occurs
every 6 milliseconds ± 1/584 milliseconds.
68
LOSW3
DI
Loop 3 Loss of Sync Word Status
. This pin inputs the LOSW status from the Loop 3
transceiver. This pin provides hardware override for the demux TMGSRC control bits,
disables Loop 3 error counters, and can force demux E1 Partial-AIS. It has an internal pull
up resistor.
69
LP3DTI
DI
Loop 3 Data In
. This signal inputs demux data, which is sampled on rising edge of ICLK1,
from the Loop 3 transceiver. The nominal bit rate of this signal is 1168 kbps.
70
RFP3
DI
Loop 3 Receive Frame Pulse
(Active Low). A Low level on this signal indicates the last bit
position of each demux HDSL frame for Loop 3. The position of this pulse is at bit 7006
when no stuffing is added, or bit 7010 when stuffing is added. This pulse nominally occurs
every 6 milliseconds ± 1/584 milliseconds.
71
VCC6
-
+5 Volt Supply
.
Table 1. Pin Descriptions (Continued)
Pin
Symbol
I/O
1
Description
1. DI = digital input; DO = digital output, DI/O = digital input and output; AI = analog input, AO = analog output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXP730LE | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| LXT1000 | LAN TRANSCEIVER|SINGLE|HYBRID|BGA|492PIN|PLASTIC |
| LXT19908 | Amplifier. Other |
| LXT300JE | PCM Transceiver |
| LXT300NE | PCM Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXP730 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Multi-Rate DSL Framer |
| LXP730LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FRAMER/FORMATTER|CMOS|QFP|64PIN|PLASTIC |
| LXP80 | 制造商:Johnson Components 功能描述: |
| LXPB2SA-50SB-Q | 制造商:SMC Corporation of America 功能描述:Actuator, electric, ball bushing |
| LXPH0000 | 制造商:Red Lion Controls 功能描述:ANNUNCIATOR LABELS, 1 LPAX LABEL: PH 制造商:Red Lion Controls 功能描述:1 LPAX LABEL PH |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。