參數(shù)資料
型號(hào)： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 15/84頁(yè)
文件大?。?/td> 1108K
代理商： LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
15
2.0
Functional Description
The framer is separated into the following blocks of logic: the multiplexer, demultiplexer,
microprocessor interface, E1 interface, and HDSL interface. The following subsections describe
each logic function.
The ETSI Technical Report ETR 152 will yield a better understanding of the ETSI HDSL system.
Framer related sections include, but are not limited to, the HDSL core specifications, frame
structure and Application specific requirements. It is beyond the scope of this document to
completely explain all of the details in ETR 152, but some of the directly related HFMA
functionality will be covered.
2.1
Multiplexer (MX)
The function of the MX block is to split the E1 payload into 2 or 3 parts and then multiplex each
part with HDSL overhead (HOH) bits, including CRC6, eoc and Z-bits to be passed on to the
individual HDSL data pumps. The MX block controls stuffing into the HDSL data stream. The MX
block configuration registers are programmed by the microprocessor. The microprocessor also sets
the eoc and Z-bits. Individual loop testing is supported by generating test and error patterns in the
MX block.
Sync word generation and data scrambling, as defined by ETR 152, are done by the SK70707
digital transceiver, and therefore are not performed by the HFMA.
Figure 3
shows a simplified logic block of the MX process. The MX_E1_CTL block uses the
selected E1 clock to load the E1 data from the E1 Interface into the FIFOs. The E1 clock may be
either the derived clock from the E1 data stream, E1CLKI, or an internal nominal clock
(E1_NMCK). The MXE1CTL register (
Table 3 on page 24
) controls which E1 clock is selected as
well as selecting whether E1 data or AIS (all 1s) is clocked into the FIFOs. The NMFMEN bit of
the MXE1CTL register, when 0, selects the E1FRMI pin, otherwise an internally generated frame
pulse is used. The Loop
n
Time Slot Control Byte registers, L
n
TSCTL
x
, listed in
Table 10
through
Table 20
, control which time slots of the E1 data stream are assigned to which HDSL loop. The
values loaded in these registers become valid only after setting the LDTABLE bit in the TSCTL
register (
Table 9 on page 28
). The MX Process HDSL loop data is routed to the HDSL Interface.
HDSL loops 2 and 3 are aligned to loop 1. The HDSL_MX block multiplexes the HOH bits with
the payload data as shown in
Table 114 on page 68
. The HOH bits consist of 19 indicator bits, 13
eoc bits, 14-bit sync word, and 4 stuffing bits (when necessary). Each loop has its own multiplexer.
A CRC6 is calculated per frame for each loop excluding the CRC bits, 14-bit sync word and the 4
stuffing bits. The result is stored and transmitted in the following frame.
The other indicator bits are febe, losd, bpv, ps1, ps2, hrp, rrbe, rcbe, rega, rta, indc/indr and uib.
The febe bit is generated from the DX process and is sent out to the far end HDSL device to
indicate that a CRC error occurred in the local received data. The losd bit is from the LOSDI pin
for loss of signal at the E1 interface. The bpv bit is from the BPVI pin for a bipolar violation in the
E1 data. The bits ps1 and ps2 are Power Status bits from NTU (HTU-R) -> LTU (HTU-C) only.
The hrp is the HDSL Repeater Present bit (repeater only). The rrbe, rcbe and rega bits are used for
the regenerator/repeater status. The rta is for the remote (NTU) alarm. The 2 uib bits are the
Unspecified Indicator Bits.
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