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參數(shù)資料
| 型號(hào)： | LXP710PE |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 40/84頁(yè) |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
40
Datasheet
Global Control Register
Address: 21
Abbreviation: GLBCTL
Read/Write
PLL Band Width Control Registers (2 bytes)
Address: 22
Abbreviation: PLL_BWH
Read/Write
Address: 23
Abbreviation: PLL_BWL
Read/Write
Table 35. Global Control Register
Bit
Name
Default
Description
7
n/a
0
Not used; always read zero.
6
LP_CFG[1]
0
HDSL loop configuration for fractional E1 application at central office side.
These two bits will control the relationship of DX three data buffer
’
s restart.
00: loops 1, 2 coming from the same remote terminal.
01: loops 1, 3 coming from the same remote terminal.
10: loops 2, 3 coming from the same remote terminal.
11: 3 loops coming from 3 different remote terminals.
5
LP_CFG[0]
0
4
E1DTLB
0
E1 Data Loopback Enable for fractional E1. When High, both input/output
directions of the E1 NRZ data are loopback, but not the E1 clock or frame
pulse. When Low, normal operation.
3
E1FMSEL
0
E1 Framer Select. 0 = Select DS2143; 1 = Select DS2181.
If 0, E1FRM0 and E1FRM1 coincide with the first bit of time slot 0 for E1DAT0
and E1DATI respectively.
If 1, E1FRM0 and E1FRMI coincide with the last bit of time slot 31 for E1DAT0
and E1DATI respectively.
2
THMODEN
1
1 = Threshold Modulation Enable.
0 = Threshold Modulation Disable.
<1:0>
TMGSTAT
0
Indicates the DX E1 clock loop source status.
00: loop 1
01: loop 2
10: loop 3
Table 36. PLL Band Width Control (High Byte)
Bit
Name
Default
Description
<7:0>
PLL_BWH
FC
PLL locking time register High byte. For values greater than 80h, longer
locking time to low end frequency, with lower jitter amplitude.
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