參數(shù)資料
型號： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 17/84頁
文件大?。?/td> 1108K
代理商： LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
17
2.2
Demultiplexer (DX)
The DX performs the reverse function of the MX by de-multiplexing the HDSL bits into HOH bits
and payload data and then combining the 2/3 HDSL payloads into an E1 payload. The HOH bits,
eoc and Z-bits, are separated out from the payload, stored into registers for the microprocessor to
read. The DX checks the received CRC6 against the data and sets a flag in case of an error
condition. The DX also provides the E1 clock based upon an internal PLL.
Figure 4
shows a simplified logic diagram of the DX Process. Each individual loop data is clocked
into a separate FIFO. The DX_E1_CTL block controls the Write Enable to the FIFOs by blocking
the HOH bits from being loaded into the FIFOs. The DX_E1_CTL selects from which FIFO to
load data. The ordering of the time slots is based on the values programmed into the L
n
TSCTL
x
registers as described in
Table 10
through
Table 20
. The values loaded in these registers become
valid only after setting the LDTABLE bit in the TSCTL register,
Table 9
. The data is passed
through a mux to DX_E1_DATA. The other selection of the mux is AIS. The use of AIS for the
outgoing E1 data is controlled by the 4 LSBs of DXE1CTL register (
Table 4
).
The DX_E1_CTL block generates a 1168KHz gapped clock as a reference for the E1_TMG_GEN
block. The DX_E1_CTL uses the DX_E1_CK from the E1_TMG_GEN to track the current
position in the outgoing E1 data stream and to generate the DX_E1_FM, E1 framing pulse.
The E1_TMG_GEN uses the DX_GAP_CK as the reference for the DX_E1_CK. The
DX_E1_NMCK is a nominal E1 clock used for E1 AIS, E1 loopback and as the source for the
NME1CKO pin to sync an E1 framer when it has no clock.
The OH_PROC, overhead processor, looks for all of the HOH bits in the incoming HDSL frames.
There is a OH_PROC block for each HDSL loop. The received Z-bits, eoc bits and overhead bits
are latched into their respective registers in the UP_IF. A CRC is calculated on the received data
and the result is stored for comparison against the CRC bits in the following frame. A CRC error
generates the febe bit to the MX Process. The OH_PROC increments the associated error counters
for CRC, febe and bpv. These counters are in the
μ
P_IF section. The sync word bits and stuffing
bits are discarded.
The OH_PROC compares the loop ID received from each loop and generates a report to the
μ
P_IF,
LPRSTAT register in
Table 28
, and sends the loop correction bits to the HDSL Interface.
The PAT_DET block, one per loop, generates a Pattern Sync Lost indication bit, PATLOS bit in
PATSTAT register (see
Table 24 on page 35
), when the sync is not present. The PAT_DET
increments the appropriate L
n
PATECL (
Table 60
,
Table 84
, and
Table 109
) counter for each
instance of a QRSS pattern bit failure. Overflows of these counters are indicated in PATSTAT
register OVERFLOW bits (
Table 24
). Overflows may also be set to trigger an interrupt via the
μ
P_IF registers GENINTEN and GENINTSTAT (
Table 29
and
Table 30
).
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