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參數(shù)資料
| 型號(hào)： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 47/84頁(yè) |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
47
Address: 3B
Abbreviation: L1PATECL
Read
Loop 1 Mux Restart Counter
Address: 3C
Abbreviation: DX1RSCNTR
Read
Mux Loop 2 Z Bit Register (6 Bytes)
Address: 45
Abbreviation: MXL2Z1
Read/Write
Address: 46
Abbreviation: MXL2Z2
Table 60. Loop 1 QRSS Test Pattern Error Counter (High byte)
Bit
Name
Default
Description
<7:0>
PAT1ECH <15:8>
0
Loop 1 Test Pattern Error Counter (High byte). This 16-bit counter increments
each time the demux test pattern receiver detects a pattern error. When the
upper byte is read, the current count of both bytes is latched and the counter
is cleared. This counter is disabled when pattern sync is lost. This counter
does not stop counting at 0FFFFh, however, a latched overflow status bit is
provided in the General Interrupt Vector Status register.
Table 61. Loop 1 QRSS Test Pattern Error Counter (Low)
Bit
Name
Default
Description
<7:0>
PAT1ECL <7:0>
Loop 1 Test Pattern Error Counter (Low byte). The lower byte is latched
when the upper byte is read. Therefore, this byte must be read last when
reading the 16-bit Pattern Error Counter.
Table 62. Loop 1 Mux Restart Counter
Bit
Name
Default
Description
<7:0>
n/a
0
Loop 1 Mux Restart Counter. Increments each time the Mux loop 1 has been
restarted. Cleared when read and stops at FFh.
Table 63. Mux Loop 2 Z Bits (LSB)
Bit
Name
Default
Description
<7:0>
Z<1:8>
FF
Mux Loop 2 Z bit <1:8>
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