參數(shù)資料
型號: LXP710PE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 41/84頁
文件大小: 1108K
代理商: LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
LXP710
Datasheet
41
Demux Restart Counter Register
Address: 24
Abbreviation: DXRSCNTR
Read only
Mux Loop 1 Z Bit Registers (6 Bytes)
Address: 25
Abbreviation: MXL1Z1
Read/Write
Address: 26
Abbreviation: MXL1Z2
Read/Write
Address: 27
Abbreviation: MXL1Z3
Read/Write
Table 37. PLL Band Width Control (Low Byte)
Bit
Name
Default
Description
<7:0>
PLL_BWL
03
PLL locking time register Low byte. For values less than 80h, longer locking
time to High end frequency, with lower jitter amplitude.
Table 38. Demux Restart Counter
Bit
Name
Default
Description
<7:0>
n/a
0
E1 Demux Restart Counter. Increments each time the E1 demux loop has
been restarted. Primarily used for manufacture testing.
Table 39. Mux Loop 1 Z Bits (LSB)
Bit
Name
Default
Description
<7:0>
Z<1:8>
FF
Mux Loop 1 Z bit <1:8>
Table 40. Mux Loop 1 Z Bits
Bit
Name
Default
Description
<7:0>
Z<9:16>
FF
Mux Loop 1 Z bit <9:16>
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