參數(shù)資料
型號(hào)： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 4/84頁
文件大小： 1108K
代理商： LXP710PE
LXP710 —
HDSL Framer/Mapper for 1168 kbps Applications
4
Datasheet
20
21
22
23
24
25
Output Wander Performance ..............................................................................80
Typical Jitter Transfer Results.............................................................................81
Jitter Transfer Measurement Setup.....................................................................81
Typical Jitter Tolerance Results..........................................................................82
Jitter Tolerance Measurement Setup..................................................................82
Plastic Leaded Chip Carrier Package Specification............................................83
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Pin Descriptions..................................................................................................11
Register Summary ..............................................................................................21
Mux E1 Control Register.....................................................................................24
Demux E1 Control Register ................................................................................25
HDSL Loop Control Register...............................................................................26
HDSL Loop 1 Overhead Control Register...........................................................26
HDSL Loop 2 Overhead Control Register...........................................................27
HDSL Loop 3 Overhead Control Register...........................................................28
Time Slot Grouping Table Control Register........................................................28
Loop 1 Time Slot Control Byte 1 .........................................................................29
Loop 1 Time Slot Control Byte 2 .........................................................................29
Loop 1 Time Slot Control Byte 3 .........................................................................30
Loop 1 Time Slot Control Byte 4 .........................................................................30
Loop 2 Time Slot Control Byte 1 .........................................................................31
Loop 2 Time Slot Control Byte 2 .........................................................................31
Loop 2 Time Slot Control Byte 4 .........................................................................32
Loop 3 Time Slot Control Byte 1 .........................................................................32
Loop 3 Time Slot Control Byte 2 .........................................................................33
Loop 3 Time Slot Control Byte 3 .........................................................................33
Loop 3 Time Slot Control Byte 4 .........................................................................33
Programmable Idle Code Bytes..........................................................................33
QRSS Test Pattern Control Register ..................................................................34
Frame Pulse Sync & PLL Control Register.........................................................34
Test Pattern Error Counter Status Register........................................................35
Demux Power Status Register............................................................................35
Demux HDSL Repeater Present Status Register ...............................................36
Demux Loss of Signal Status Register................................................................36
Loop Reversal Status Register ...........................................................................36
General Interrupt Enable Register ......................................................................37
General Interrupt Status Register .......................................................................37
6ms Interrupt Enable Register ............................................................................38
6ms Interrupt Status Register .............................................................................38
Indicator Bits & Triple Echo EOC Enable Register .............................................39
Indicator Bits & Triple EOC Status Register........................................................39
Global Control Register.......................................................................................40
PLL Band Width Control (High Byte)..................................................................40
PLL Band Width Control (Low Byte) ..................................................................41
Demux Restart Counter .....................................................................................41
Mux Loop 1 Z Bits (LSB).....................................................................................41
Mux Loop 1 Z Bits...............................................................................................41
Mux Loop 1 Z Bits...............................................................................................42
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