參數(shù)資料
型號(hào)： LXP710PE
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 66/84頁(yè)
文件大?。?/td> 1108K
代理商： LXP710PE
LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
66
Datasheet
4.4.1
Board Initialization
This is usually the first code run which initializes the microprocessor which in turn writes the
desired starting values to all the registers in the devices on the board. Configuration switches are
read to determine whether the board is: a LTU or NTU unit, full 2M or fractional, etc.
After this phase is complete the LTU board can communicate with its master controller in the rack.
This is necessary to receive channel configuration and report the status of the loop. The OEM can
decide whether the LTU should automatically activate the loops or wait for a explicit command
from the rack controller.
4.4.2
Loop Activation
This phase prepares the loops to carry the payload, in this case E1 data. The data pumps must go
through a sophisticated process of training the receivers for echo cancellation, channel equalization
and level slicing adjustment. Fortunately Intel data pumps do this automatically by just setting the
Activation Request bit in the Control register. When the Active State bit in the Status register is set,
this process is complete. Interrupt generation can be used to free the processor from polling to
determine completion. Intel data pumps also automatically detect and correct TIP/RING polarity
reversal in the wire pair connection.
Once the data pumps are able to pass data, the framers take over to establish communication
between the LTU and NTU. The first step is to establish that the loop wire pairs are connected
correctly. The LTU sets Z-bits 1 - 3 to indicate loop identification. This is done by writing to the
MX Z-bit registers. The NTU receives the loop IDs on the individual loops and checks to see if
they are correct, if not then the NTU framer must switch the data paths internally to match and then
set its MX loop ID back to the LTU when this process is complete. The loop reversal detect and
switch can be done automatically in the LXP710 by setting the LPREN
x
bits in the TSCTL (06h)
register during the board initialization phase.
The second step for each side to set its MX indc/r bit when it is ready to receive data.
The loop
x
time slot control bytes must be set. Default values can be stored at the LTU and NTU
boards and loaded at power up. Alternately the LTU could receive the assignment from the rack
master and, after receiving the indr bit from the NTU, send the configuration to the NTU using the
unused Z-bits. Each loop could receive its assignment on its own loop. There is no standard for
how the time slot assignments are made remotely so the OEM must take care to be consistent in
future equipment designs to maintain interoperability.
4.4.3
Normal Operation
Payload data is transported to both sides in this mode.
Additionally this mode monitors the condition of the HDSL system. Operational characteristics
such as signal-to-noise ratio (SNR), loss of signal (LOS) and CRC errors are tracked on each loop
to anticipate problems. A LOSW from a data pump is a definite indication that the loop is
malfunctioning and corrective action must be taken.
When symptoms indicate that corrective actions are needed, the HDSL system should make
changes gracefully to minimize the effect on the E1 link. In the instance of HDSL loop failures the
LTU should continually cycle through activation attempts, while the NTU should go QUIET, time-
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