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參數資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 36/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
36
Datasheet
Read/Write
Note:
Although the HDSL overhead indicator bits are active Low on the HDSL data stream, all status bits
in this register are active High, i.e., the status bits are inverted from what was received on the loop.
Demux Loss of Signal Status Register
Address: 19
Abbreviation: DXLOSDSTAT
Read/Write
All of the HDSL overhead status bits in this register are latched active High when detected, and
remain High until a write of a logic one is done by the microprocessor.
Note:
Although the HDSL overhead indicator bits are active Low on the HDSL data stream, all status bits
in this register are active High, i.e., the status bits are inverted from what was received on the loop.
Loop Reversal Status Register
Address: 1A
Abbreviation: LPRSTAT
Read/Write
Table 26. Demux HDSL Repeater Present Status Register
Bit
Name
Default
Description
<7:3>
n/a
0
Not used; Always read Low.
<2:0>
D<3:1>HRP
0
Demux loop<3:1> HDSL Repeater present status bit.
Table 27. Demux Loss of Signal Status Register
Bit
Name
Default
Description
<7:3>
n/a
0
Not used; Always read Low.
<2:0>
D<3:1>LOSD
0
Demux loop<3:1> loss of signal status bit.
Table 28. Loop Reversal Status Register
Bit
Name
Default
Description
7, 6
n/a
0
Not used; Always read zero.
5
LPRDONE3
0
Loop Reversal Detect. When in HTUC Mode (LTU = 1), Loop
x
has detected
the loop identification returned from HTUR.
In HTUR Mode (LTU = 0), Loop
x
has detected the same loop identification
three times, and the Loop
x
reversal is done.
4
LPRDONE2
0
3
LPRDONE1
0
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