參數(shù)資料
型號： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 63/84頁
文件大?。?/td> 1108K
代理商： LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
—
LXP710
Datasheet
63
4.3
User Definable HDSL Overhead Bits
ETSI specifications allocate overhead bits with the intent of command and control between the
LTU (HTU-C) and NTU (HTU-R) units. The eoc bits are primarily used for this; plus three Z-bits
for loop identification. The remaining 45 Z-bits per 6ms frame per loop are open for any use. This
yields a 7.5 kbps channel per loop in both directions for data or low quality voice. If ETSI
compliance is not needed, then the additional 13 eoc and 2 uib bits per frame bring this value to 10
kbps. This extra channel is accessible by the microprocessor with interrupts provided at the frame
rate per loop to coordinate the writing to and reading of this channel. A point-to-point system could
pair up these channels to provide a 15 kbps channel ETSI compliant, and a 20 kbps non ETSI
compliant channel.
Figure 7. Two-Loop E1 HDSL System
Data Pump 2
Data Pump 1
LXT305A
E1 LIU
DS2181A
E1 Framer
LXP710
SK70707/8
HDX
SK70707/8
HDX
SK70704
ACC
SK70704
ACC
Microprocessor
E1 Line
HDSL Lines
RTIP
RRING
TTIP
TRING
RPOS
RNEG
RCLK
TCLK
TPOS
TNEG
TPOS
TNEG
TCLK
RCLK
RNEG
RPOS
TSER
TFSYNC
RSER
RFSYNC
TDATA
TFP
RDATA
RFP
LOSW
ICLK
ICLK
LOSW
RFP
RDATA
TFP
TDATA
LP2DTO
TFP2
LP2DTI
RFP2
LOSW2
ICLK2
ICLK1
LOSW1
LP1DTI
RFP1
TFP1
LP1DTO
E1DATI
E1FRMI
E1CLKI
E1CLKO
E1DATO
E1FRMO
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