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參數(shù)資料
| 型號： | LXP710PE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 12/84頁 |
| 文件大?。?/td> | 1108K |
| 代理商： | LXP710PE |
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LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
12
Datasheet
25
TSTMD2
DI
Test Mode 2
. This Input should be tied Low and is reserved for factory test modes.
26
27
28
29
30
31
32
A6
A5
A4
A3
A2
A1
A0
DI
DI
DI
DI
DI
DI
DI
Microprocessor Address Bus
. This 7-bit input bus is used by the microprocessor to
select LXP710 registers for read/write data transfer.
33
CS
DI
Chip Select
(Active Low). This input must be Low to enable read or write access to the
LXP710.
34
R/
W
(
WR)
DI
Read/Write or Write Enable
. In Intel mode, enables a write cycle when Low. In Motorola
mode, this signal functions as the Read/Write control. The D<7:0> bus contents are
latched into the addressed register when
WR
and
CS
are Low.
35
VCC3
-
+5 Volt Supply
.
36
CLK32M
DI
External Reference Clock
. Requires a 32.768 MHz ±50 ppm input for internal PLL.
37
GND3
-
Ground
.
38
FT2
-
Factory Test
. This pin should not be connected and is reserved for factory test.
39
FMOUT
DO
Frame Pulse Output
. This output pin provides an 6 ms, active High, frame pulse selected
from one of
RFP1
,
RFP2
, or
RFP3
for an external PLL circuit.
40
NME1CKO
DO
External Reference Clock.
2.048 Mhz reference for E1 framer and LIU when E1 input
has no clock.
41
VCC4
-
+5 Volt Supply
.
42
EXPLLI
DI
External PLL Input
. This input clock pin accepts a 2.048 MHz phase locked clock from an
external PLL circuit.
43
GND4
-
Ground
.
44
LP1DTO
DO
Loop 1 Data Output
. This pin outputs mux data, which is updated on falling edge of
ICLK1, to the Loop 1 transceiver. The nominal bit rate of this signal is 1168 kbps.
45
TFP1
DO
Loop 1 Transmit Frame Pulse
(Active Low). A Low level on this signal indicates the last
bit position of each mux HDSL frame for Loop 1. The position of this pulse is at bit 7006
when no stuffing is added, or bit 7010 when stuffing is added. This pulse nominally occurs
every 6 milliseconds ± 1/584 milliseconds.
46
LOSW1
DI
Loop 1 Loss of Sync Word Status
. This pin inputs the LOSW status from the Loop 1
transceiver. This pin provides hardware override for the demux TMGSRC control bits,
disables Loop 1 error counters, and can force demux E1 Partial-AIS. (If EXTDXAIS bit
enabled). It has an internal pull up resistor, and is active High.
47
LP1DTI
DI
Loop 1 Data In
. This signal inputs demux data, which is sampled on rising edge of ICLK1,
from the Loop 1 transceiver. The nominal bit rate of this signal is 1168 kbps.
48
RFP1
DI
Loop 1 Receive Frame Pulse
(Active Low). A Low level on this signal indicates the last bit
position of each demux HDSL frame for Loop 1. The position of this pulse is at bit 7006
when no stuffing is added, or bit 7010 when stuffing is added. This pulse nominally occurs
every 6 milliseconds ± 1/584 milliseconds.
49
FT4
-
Factory Test
. This pin should not be connected and is reserved for factory test.
50
ICLK1
DI
Loop 1 Transceiver Interface Clock
. This clock input synchronizes the transfer of HDSL
data and frame mark to/from the Loop 1 transceiver. This clock samples the LP1DTI and
RFP1
inputs on rising edge, and outputs the LP1DTO and
TFP1
outputs on the falling edge.
The nominal frequency of this clock signal is 1168 kHz.
Table 1. Pin Descriptions (Continued)
Pin
Symbol
I/O
1
Description
1. DI = digital input; DO = digital output, DI/O = digital input and output; AI = analog input, AO = analog output.
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