PRODUCT BRIEF
GiGA
10Gbit/s Limiting Amplifier Device
LXT19908
Product Description
GiGA
, an Intel company, has developed the LXT19908
wide bandwidth Limiting Amplifier (LIA) device for use
in SDH STM-64, SONET OC-192, G.709, DWDM and
10GE receiver applications in optical communication
systems. The LXT19908 has a high dynamic range,
providing linear gain higher than 40dB.
The high input sensitivity LIA accepts input signals
below 2Vpp differential and tolerates a maximum of
1Vpp for single-ended applications. The output swing
is adjusted by the Voltage Output (VSET) control and
can be varied between 0 and 1Vpp, which facilitates
interoperability between CDR and DEMUX components.
The input and output ports are internally terminated
at 50
, and an external offset control can be imple-
mented to optimize sensitivity of the CDR.
Low power dissipation is approximately 260–800mW,
depending on the output swing (no heat sink required).
The LXT19908 is assembled in a 16-pin 5.8 x 5.8 mm
ceramic QFP package, using small form factor design
to reduce the overall size of the PCB.
The LXT19908 is manufactured in a proven GaAs tech-
nology, offering the performance, stability, and reliability
customers require for optical communication systems.
Flexible Input/Output Design
The GiGA LXT19908 inputs may be either AC- or DC-
coupled, with input termination through VINREF/VINREFN
pins as shown in Figure 1. If the inputs are AC coupled,
the LXT19908 features internal DC offset compensa-
tion. The outputs have 50
termination internally and
can also be AC- or DC-coupled.
When single-ended input is required, the unused input
should be terminated with 50
to ground. For optimal
sensitivity, of the decision circuit following the LXT19908,
an external offset control can be applied. This works
with both DC- and AC-coupled inputs, as well as
single-ended and differential configurations.
Key Applications
SDH STM-64
SONET OC-192
DWDM systems
10Gbit/s Ethernet receivers
OTN,
10Gbit/s FEC with up to 25
% overhead
VOUT
VIN
VINREF
VINREFN
VINN
VSET
VOUTN
GND
VEE
Figure 1. Input/Output Schematic