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參數資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數： | 98/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
(2) EPP ADDRESS READ
1. The Host reads a byte from the EPP Address Port. The chip drives the PD bus to tri-state for the
peripheral to drive.
2. The chip drives IOCHRDY low and asserts ASTB# after IOR is active.
3. Peripheral drives the PD bus valid and deasserts WAIT#, indicating that the chip may begin to terminate
this cycle. The chip then deasserts ASTB#, latches the address from PD bus to D0 -D7 and releases
IOCHRDY, allowing the Host to complete the I/O READ cycle.
4. Peripheral drives the PD bus to tri-state and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
(3) EPP DATA WRITE
1. The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto
PD0 -PD7.
2. The chip drives IOCHRDY low and asserts WRITE# (STB#) and DSTB#(AFD#) after IOW becomes
active.
3. The peripheral deasserts WAIT#, indicating that the chip may begin the termination of this cycle. The
chip then deasserts DSTB#, latches the data from D0 - D7 to the PD bus and releases IOCHRDY,
allowing the Host to complete the I/O WRITE cycle.
4. The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. The chip
then deasserts WRITE to terminate the cycle.
(4) EPP DATA READ
1. The Host reads a byte from the EPP DATA Port. The chip drives PD bus to tri-state for peripheral to
drive.
2. The chip drives IOCHRDY low and asserts DSTB# after IOR is active.
3. The peripheral drives PD bus valid and deasserts WAIT#, indicating that the chip may begin the
termination of this cycle. The chip then deasserts DSTB#, latches the data from PD bus to D0 - D7 and
releases IOCHRDY allowing the host to complete the I/O READ cycle.
4. The peripheral tri-states the PD bus and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
11.6.3 ECP Mode
This mode is both software and hardware compatible with the existing parallel ports, allowing ECP to be
used as a standard LPT port when ECP is not required. It provides an automatic high-burst-bandwidth
channel that supports DMA or ECP mode in both forward and reverse directions. A 16-byte FIFO is
implemented in both forward and reverse directions to smooth data flow and enhance the maximum
bandwidth allowed. The port supports an automatic handshaking for the standard parallel port to improve
compatibility and increase the speed of mode transfer. It also supports run-length encoded (RLE)
decompression in hardware. Compression is accomplished by counting identical bytes and transmitting an
RLE byte that indicates how many times a byte has been repeated. The IT8673F does not support
hardware RLE compression. Please refer to "Extended Capabilities Port Protocol and ISA Interface
Standard" for a detailed description.
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相關PDF資料 |
PDF描述 |
|---|---|
| IT8687R | GT 35C 35#12 SKT PLUG |
| ITC1000 | GT 85C 85#16 SKT PLUG |
| ITF86130SK8T | N-Channel, Logic Level, Power MOSFET(N溝道邏輯電平功率MOS場效應管) |
| ITF86182SK8T | 11A, 30V, 0.0115 Ohm, P-Channel, Logic Level, Power MOSFET |
| ITF87012SVT | 6A, 20V, 0.035 Ohm, N-Channel,2.5V Specified Power MOSFET(6A, 20V, 0.035Ω N溝道2.5V專用功率MOS場效應管) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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