- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383185 > IT8673F (Electronic Theatre Controls, Inc.) GT 35C 35#12 SKT PLUG PDF資料下載
參數(shù)資料
| 型號(hào)： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級(jí)I / O）的初步規(guī)范V0.5 |
| 文件頁(yè)數(shù)： | 98/128頁(yè) |
| 文件大小： | 780K |
| 代理商： | IT8673F |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)當(dāng)前第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
IT8673F
(2) EPP ADDRESS READ
1. The Host reads a byte from the EPP Address Port. The chip drives the PD bus to tri-state for the
peripheral to drive.
2. The chip drives IOCHRDY low and asserts ASTB# after IOR is active.
3. Peripheral drives the PD bus valid and deasserts WAIT#, indicating that the chip may begin to terminate
this cycle. The chip then deasserts ASTB#, latches the address from PD bus to D0 -D7 and releases
IOCHRDY, allowing the Host to complete the I/O READ cycle.
4. Peripheral drives the PD bus to tri-state and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
(3) EPP DATA WRITE
1. The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto
PD0 -PD7.
2. The chip drives IOCHRDY low and asserts WRITE# (STB#) and DSTB#(AFD#) after IOW becomes
active.
3. The peripheral deasserts WAIT#, indicating that the chip may begin the termination of this cycle. The
chip then deasserts DSTB#, latches the data from D0 - D7 to the PD bus and releases IOCHRDY,
allowing the Host to complete the I/O WRITE cycle.
4. The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. The chip
then deasserts WRITE to terminate the cycle.
(4) EPP DATA READ
1. The Host reads a byte from the EPP DATA Port. The chip drives PD bus to tri-state for peripheral to
drive.
2. The chip drives IOCHRDY low and asserts DSTB# after IOR is active.
3. The peripheral drives PD bus valid and deasserts WAIT#, indicating that the chip may begin the
termination of this cycle. The chip then deasserts DSTB#, latches the data from PD bus to D0 - D7 and
releases IOCHRDY allowing the host to complete the I/O READ cycle.
4. The peripheral tri-states the PD bus and then asserts WAIT#, indicating that it acknowledges the
termination of the cycle.
11.6.3 ECP Mode
This mode is both software and hardware compatible with the existing parallel ports, allowing ECP to be
used as a standard LPT port when ECP is not required. It provides an automatic high-burst-bandwidth
channel that supports DMA or ECP mode in both forward and reverse directions. A 16-byte FIFO is
implemented in both forward and reverse directions to smooth data flow and enhance the maximum
bandwidth allowed. The port supports an automatic handshaking for the standard parallel port to improve
compatibility and increase the speed of mode transfer. It also supports run-length encoded (RLE)
decompression in hardware. Compression is accomplished by counting identical bytes and transmitting an
RLE byte that indicates how many times a byte has been repeated. The IT8673F does not support
hardware RLE compression. Please refer to "Extended Capabilities Port Protocol and ISA Interface
Standard" for a detailed description.
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IT8687R | GT 35C 35#12 SKT PLUG |
| ITC1000 | GT 85C 85#16 SKT PLUG |
| ITF86130SK8T | N-Channel, Logic Level, Power MOSFET(N溝道邏輯電平功率MOS場(chǎng)效應(yīng)管) |
| ITF86182SK8T | 11A, 30V, 0.0115 Ohm, P-Channel, Logic Level, Power MOSFET |
| ITF87012SVT | 6A, 20V, 0.035 Ohm, N-Channel,2.5V Specified Power MOSFET(6A, 20V, 0.035Ω N溝道2.5V專用功率MOS場(chǎng)效應(yīng)管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。