參數(shù)資料
型號： IT8673F
廠商： Electronic Theatre Controls, Inc.
英文描述： GT 35C 35#12 SKT PLUG
中文描述： 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5
文件頁數(shù)： 16/128頁
文件大?。?/td> 780K
代理商： IT8673F
IT8673F
6. IT8673F Pin Descriptions
6
Table 6-1. Signal Names (by pin numbers in alphabetical order)
Pin(s) No.
Supplies
35, 67, 121
99
97
4,10,43, 77,
104
ISA Bus Interface Signals
21-32
SA[0:11]
Signal
I/O
Power
Description
VCC
VCCH
VBAT
GNDD
PWR
PWR
PWR
GND
-
-
-
-
+5V Digital Power Supply.
+5V VCC Help Supply.
+3.3V Battery Supply.
Digital Ground.
DI
VCC
ISA Address 0 - 11.
Input signals used to determine which internal
register is accessed. SA0-SA11 are ignored during a DMA access.
ISA Address 15 / FAN Control Output 3.
The default function of this pin is ISA address 15.
The second function of this pin is the
FAN
Control Output 3.
The function of this pin is decided by the power-on strapping of
DTR1#.
ISA Address 14 / FAN Tachometer Input 3.
The default function of this pin is ISA address 14.
The second function of this pin is the
FAN
Tachometer Input 3. (0
to +5V amplitude
FAN
tachometer input).
The function of this pin is decided by the power-on strapping of
RTS1#.
ISA Address 13 - 12.
Input signals used to determine which internal
register is accessed. SA13-SA12 are ignored during a DMA access.
ISA Data 0 - 7.
8-bit bi-directional data lines used to transfer data
between IT8673F and the CPU or DMA controller. SD0 is the LSB
and SD7 is the MSB.
Address Enable
. AEN is used to disable the internal address
decoder when it is high. This pin is always ignored during DMA
accesses.
DMA Request 1 - 3.
Active high outputs to signal the DMA controller
that a data transfer from IT8673F is required.
DMA Acknowledge 1 - 3 #.
Active low inputs to acknowledge the
corresponding DMA requests and enable the RD or WR signals
during a DMA access cycle.
PCI Clock
.
the PCI CLOCK input.
Serial Interrupt
.
Reset
.
A high level on this input resets IT8673F. This signal
asynchronously terminates any activity and places the device in the
Disable state.
I/O Read #
.
Active low input asserted by the CPU or DMA controller
to read data or status information from IT8673F.
Terminal Count
.
This input is asserted by the DMA controller to
indicate the end of a DMA transfer. The signal is only effective during
a DMA access cycle.
I/O Write #.
Active low input asserted by the CPU or DMA controller
to write data or control information to IT8673F.
I/O Channel Ready.
Pulled low to extend the Read/Write command
under the EPP mode.
96
SA15/
FAN_CTL3
DI/
DOD8
VCCH
95
SA14/
FAN_TAC3
DI/DI
VCCH
92-91
SA[13:12]
DI
VCCH
39 - 42,
44 - 47
SD[0:7]
DIO24
VCC
118
AEN
DI
VCC
74 - 76
DRQ[1:3]
DO8
VCC
87 – 89
DACK[1:3]#
DI
VCCH
36
34
119
PCICLK
SIRQ
RESET
DI
VCC
VCC
VCC
DIO24
DI
37
IOR#
DI
VCC
120
TC
DI
VCC
38
IOW#
DI
VCC
33
IOCHRDY
DOD24
VCC
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