參數(shù)資料
型號： IT8673F
廠商： Electronic Theatre Controls, Inc.
英文描述： GT 35C 35#12 SKT PLUG
中文描述： 先進的輸入/輸出（高級I / O）的初步規(guī)范V0.5
文件頁數(shù)： 109/128頁
文件大?。?/td> 780K
代理商： IT8673F
IT8673F
11.8.4 Transmit Operation
The data written to the Transmitter FIFO will be exactly serialized from LSB to MSB, modulated with carrier
frequency and sent to the CIRTX output. The data are either in bit-string format or run-length decode.
Before the data transmission can begin, code byte write operations must be performed to the Transmitter
FIFO DR. The bit TXRLE in the TCR1 should be set to “1” before the run-length decode data can be written
into the Transmitter FIFO. Setting TXENDF in the TCR1 will enable the data transmission deferral, and
avoid the transmitter FIFO underrun. The bit width of the serialized bit string is determined by the value
programmed in the baud rate divisor registers BDLR and BDHR. When the bits HCFS and CFQ[4:0] are
set, either the high-speed or low-speed carrier range is selected, and the corresponding carrier frequency
will also be determined. Bits TXMPM[1:0] and TXMPW[2:0] specify the pulse numbers in a bit width and
the required duty cycles of the carrier pulse according to the communication protocol. Only a logic “0” can
activate the Transmitter LED in the format of a series of modulating pulses.
11.8.5 Receive Operation
The Receiver function is enabled if the bit RXEN in the RCR is set to “1”. Either demodulated or modulated
RX# signal is loaded into the Receiver FIFO, and the bit RXEND in the RCR determines the demodulation
logic should be used or not. Determine the baud rate by programming the baud rate divisor registers BDLR
and BDHR, and the carrier frequencies by programming the bits HCFS and CFQ[4:0]. Set RDWOS to “0”
to sync. The bit RXACT in the RCR is set to “1” when the serial data or the selected carrier are incoming,
and the sampled data will then be kept in the Receiver FIFO. Write “1” to the bit RXACT to stop the
Receiver operation; “0” to the bit RXEN to disable the Receiver.
11.8.6 Register Descriptions and Address
9
Table 11-46. List of CIR Registers
Address
R/W
Default
Name
Base + 0h
R/W
FFh
CIR Data Register (DR)
Base + 1h
R/W
00h
CIR Interrupt Enable Register (IER)
Base + 2h
R/W
01h
CIR Receiver Control Register (RCR)
Base + 3h
R/W
00h
CIR Transmitter Control Register 1 (TCR1)
Base + 4h
R/W
5Ch
CIR Transmitter Control Register 2 (TCR2)
Base + 5h
R
00h
CIR Transmitter Status Register (TSR)
Base + 6h
R
00h
CIR Receiver Status Register (RSR)
Base + 5h
R/W
00h
CIR Baud Rate Divisor Low Byte Register (BDLR)
Base + 6h
R/W
00h
CIR Baud Rate Divisor High Byte Register (BDHR)
Base + 7h
R/W
01h
CIR Interrupt Identification Register (IIR)
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IT86C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220
IT86F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220
IT86G 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220
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