參數(shù)資料
型號: IT8673F
廠商: Electronic Theatre Controls, Inc.
英文描述: GT 35C 35#12 SKT PLUG
中文描述: 先進的輸入/輸出(高級I / O)的初步規(guī)范V0.5
文件頁數(shù): 89/128頁
文件大小: 780K
代理商: IT8673F
IT8673F
9
Table 11-31. Line Control Register Description
Bit
Default
Description
7
0
Divisor Latch Access Bit (DLAB)
Must be set to high to access the Divisor Latches of the baud rate generator
during READ or WRITE operations. It must be set low to access the Data
Register (RBR and TBR) or the Interrupt Enable Register.
Set Break
Forces the Serial Output (SOUT) to the spacing state (logic 0) by a logic 1, and
this state will be preserved until a low level resetting LCR(6), enabling the
serial port to alert the terminal in a communication system.
Stick Parity
When this bit and LCR(3) are high at the same time, the parity bit is
transmitted, and then detected by receiver, in opposite state by LCR(4) to
force the parity bit into a known state and to check the parity bit in a known
state.
Even Parity Select
When parity is enabled (LCR(3) = 1), LCR(4) = 0 selects odd parity, and
LCR(4) = 1 selects even parity.
Parity Enable
A parity bit, located between the last data word bit and stop bit, will be
generated or checked (transmit or receive data) when LCR(3) is high.
Number of Stop Bits
Specifies the number of stop bits in each serial character, as summarized in
table 11-32.
Word Length Select [1:0]
11: 8 bits
10: 7 bits
01: 6 bits
00: 5 bits
6
0
5
0
4
0
3
0
2
0
1-0
00
Table 11-32. Stop Bits Number Encoding
LCR (2)
Word Length
No. of Stop Bits
0
-
1
1
5 bits
1.5
1
6 bits
2
1
7 bits
2
1
8 bits
2
Note
: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmission.
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