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參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 94/128頁 |
| 文件大小： | 780K |
| 代理商： | IT8673F |
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IT8673F
4
RCVR FIFO time-out Interrupt: By enabling the RCVR FIFO and receiver interrupts, the RCVR FIFO
time-out interrupt will occur under the following conditions:
a. The RCVR FIFO time-out interrupt will occur only if there is at least one character in the FIFO whenever
the interval between the most recent received serial character and the most recent Host READ from the
FIFO is longer than four consecutive character times
b. The RLCK clock signal input is used to calculate character times
c. The time-out timer will be reset after receiving a new character or after the Host reads the RCVR FIFO
whenever any time-out interrupt occurs. The timer will be reset when the Host reads one character from
the RCVR FIFO
(2) XMIT Interrupt
By setting FCR(0) and IER(1) to high, the XMIT FIFO and transmitter interrupts are enabled, and the XMIT
interrupt occurs under the conditions described below:
a. The transmitter interrupt occurs when the XMIT FIFO is empty, and it will be reset if the THR is written or
the IIR is read.
b. The transmitter FIFO empty indications will be delayed one character time minus the last stop bit time
whenever the following condition occurs: THRE = 1 and there have not been at least two bytes in the
transmitter FIFO at the same time since the last THRE = 1. The transmitter interrupt after changing
FCR(0) will be immediate, if it is enabled. Once the first transmitter interrupt is enabled, the THRE
indication is delayed one character time minus the last stop bit time.
The character time-out and RCVR FIFO trigger level interrupts are in the same priority order as the received
data available interrupt. The XMIT FIFO empty is in the same priority as the transmitter holding register
empty interrupt.
FIFO Polled Mode Operation [FCR(0)=1, and IER(0), IER(1), IER(2), IER(3) or all are “0”]
Either or both XMIT and RCVR can be in this operation mode. The operation mode can be programmed by
users and is responsible for checking the RCVR and XMIT status via the LSR described below:
LSR(7): RCVR FIFO error indication
LSR(6): XMIT FIFO and Shift register empty
LSR(5): The XMIT FIFO empty indication
LSR(4) - LSR(1): Specify that errors have occurred. Character error status is handled in the same way as in
the interrupt mode. The IIR is not affected since IER(2)=0.
LSR(0): This bit is high whenever the RCVR FIFO contains at least one byte.
No trigger level is reached or time-out condition indicated in the FIFO Polled Mode.
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PDF描述 |
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| ITF86182SK8T | 11A, 30V, 0.0115 Ohm, P-Channel, Logic Level, Power MOSFET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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