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參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 84/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
11.5 Serial Port (UART) Description
The IT8673F incorporates two enhanced serial ports that perform serial to parallel conversion on received
data, and parallel to serial conversion on transmitted data. Each of the serial channels individually contains
a programmable baud rate generator which is capable of dividing the input clock by a number ranging from
1 to 65535. The data rate of each serial port can also be programmed from 115.2K baud down to 50 baud.
The character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd, stick or no parity;
and privileged interrupts.
4
Table 11-25. Serial Channel Registers
Register
Data
Control
DLAB*
0
0
x
x
x
1
1
x
x
x
Address
Base + 0h
Base + 1h
Base + 2h
Base + 3h
Base + 4h
Base + 0h
Base + 1h
Base + 5h
Base + 6h
Base + 7h
READ
WRITE
RBR (Receiver Buffer Register)
IER (Interrupt Enable Register)
IIR (Interrupt Identification Register)
LCR (Line Control Register)
MCR (Modem Control Register)
DLL (Divisor Latch LSB)
DLM (Divisor Latch MSB)
LSR (Line Status Register)
MSR (Modem Status Register)
SCR (Scratch Pad Register)
TBR (Transmitter Buffer Register)
IER
FCR (FIFO Control Register)
LCR
MCR
DLL
DLM
LSR
MSR
SCR
Status
* DLAB is bit 7 of the Line Control Register.
11.5.1 Data Registers
The TBR and RBR individually hold from five to eight data bits. If the transmitted data is less than eight bits,
it aligns to the LSB. Either received or transmitted data is buffered by a shift register, and is latched first by
a holding register. The bit 0 of any word is first received and transmitted.
(1) Receiver Buffer Register (RBR) (Read only, Address offset=0, DLAB=0)
This register receives and holds the incoming data. It contains a non-accessible shift register which
converts the incoming serial data stream into a parallel 8-bit word.
(2) Transmitter Buffer Register (TBR) (Write only, Address offset=0, DLAB=0)
This register holds and transmits the data via a non-accessible shift register, and converts the outgoing
parallel data into a serial stream before transmission.
11.5.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR and MCR
(1) Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0)
The IER is used to enable (or disable) four active high interrupts which activate the interrupt outputs with its
lower four bits: IER(0), IER(1), IER(2), and IER(3).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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