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| 型號(hào)： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級(jí)I / O）的初步規(guī)范V0.5 |
| 文件頁(yè)數(shù)： | 87/128頁(yè) |
| 文件大小： | 780K |
| 代理商： | IT8673F |
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IT8673F
(3) FIFO Control Register (FCR) (Write Only, Address offset=2)
This register is used to enable/clear the FIFO, and set the RCVR FIFO trigger level.
7
Table 11-28. FIFO Control Register Description
Bit
Default
Description
7-6
-
Receiver Trigger Level Select
These bits set the trigger levels for the RCVR FIFO interrupt.
Reserved
This bit doesn't affect the Serial Channel operation. RXRDY and TXRDY
functions are not available on this chip.
Transmitter FIFO Reset
This self-clearing bit clears all contents of the XMIT FIFO and resets its
related counter to 0 via a logic "1."
Receiver FIFO Reset
Setting this self-clearing bit to a logic “1” clears all contents of the RCVR FIFO
and resets its related counter to 0 (except the shift register).
FIFO Enable
XMIT and RCVR FIFO are enabled when this bit is set high. XMIT and RCVR
FIFOs are disabled and cleared respectively when this bit is cleared to low.
This bit must be a logic 1 if the other bits of the FCR are written to, or they will
not be properly programmed. When this register is switched to non-FIFO
mode, all its contents are cleared.
5-4
0
3
0
2
0
1
0
0
0
Table 11-29. Receiver FIFO Trigger Level Encoding
FCR (7)
FCR (6)
RCVR FIFO Trigger Level
0
0
1 byte
0
1
4 bytes
1
0
8 bytes
1
1
14 bytes
(4) Divisor Latches (DLL, DLM) (Read/Write, Address offset=0,1, DLAB=0)
Two 8-bit Divisor Latches (DLL and DLM) store the divisor values in a 16-bit binary format. They are loaded
during the initialization to generate a desired baud rate.
(5) Baud Rate Generator (BRG)
Each serial channel contains a programmable BRG which can take any clock input (from DC to 3 MHz) to
generate standard ANSI/CCITT bit rates for the channel clocking with an external clock oscillator. The DLL
or DLM is a number of 16-bit format, providing the divisor range from 1 to 2
The output frequency is 16X data rate.
16
to obtain the desired baud rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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