
IT8673F
1
51
Table 11-6. Data Rate Select Register (DSR)
Bit
Symbol
Name
Description
7
S/W
RESET
POWER
DOWN
Software Reset Software Reset. It is active high and shares the same function with the
RESET# of the DOR except that this bit is self-clearing.
Power Down
When this bit is written with a “1”, the floppy controller is put into manual low
power mode. The clocks of the floppy controller and data separator circuits
will be turned off until a software reset or the Data Register or Main Status
Register is accessed.
Not Used
-
Precompensation
Select
precompensation that will be applied to the WDATA# pin. Track 0
is the default starting track number, which can be changed by the
CONFIGURE command for precompensation.
PRE_COMP Precompensation Delay
111
001
010
011
100
101
110
000
Default Precompensation Delays
Data Rate
Precompensation Delay
1Mbps
500Kbps
300Kbps
250Kbps
125.0 ns
Data Rate
Select
00
01
10
11
6
5
NU
4-2
PRE-COMP
2-0
These three bits are used to determine the value of write
0.0 ns
41.7 ns
83.3 ns
125.0 ns
166.7 ns
208.3 ns
250.0 ns
Default
41.7 ns
125.0 ns
125.0 ns
1-0
DRATE1-0
Bits 1-0
Data Transfer Rate
500 Kbps
300 Kbps
250 Kbps (default)
1 Mbps
11.4.8.5 Data Register (FIFO, FDC Base Address + 05h)
This is an 8-bit
read/write
register. It transfers command information, diskette drive status information, and
the result phase status between the host and the FDC. The FIFO consists of several registers in a stack.
Only one register in the stack is permitted to transfer information or status to the data bus at a time.
Table 11-7. Data Register (FIFO)
Bit
Symbol
Name
Description
7-0
Data
Command information, diskette drive status, or result phase status data.