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參數(shù)資料
| 型號(hào)： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級(jí)I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 104/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
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of the transfer state. To avoid bugs during handshaking, these guidelines must be followed.
(15) Software Operation (ECP)
Before the ECP operation can begin, it is first necessary for the Host to switch the mode to 000 to
negotiate with the parallel port. Host determines whether the peripheral supports the ECP protocol during
the process.
After the negotiation is completed, the mode is set to 011 (ECP). To enable the drivers, the direction must
be set to 0. Both strobe and autoFd are set to 0, causing the nStrobe and nAutoFd signals to be
deasserted.
All FIFO data transfers are PWord wide and PWord aligned. Permitted only in the forward direction,
Address/RLE transfers are byte-wide. ECP address/RLE bytes may be automatically transmitted by
writing to the ecpAFifo. Similarly, data PWords may be sent automatically via the ecpDFifo.
To change directions, the Host switches mode to 001. It then negotiates either the forward or reverse
channel, sets direction to “1” or “0”, and finally switches mode to 001. If the direction is set to 1, the
hardware performs a handshaking for each ECP data byte READ, and tries to fill the FIFO. At this time,
PWords may be read from the ecpDFifo while it retains data. It is also possible for the hardware to perform
the ECP transfers by handshaking with individual bytes under programmed control in mode = 001, or 000,
even though this is a comparatively time-consuming approach.
(16) Hardware Operation (DMA)
The Standard PC DMA protocol is followed. As in the programmed I/O case, the software sets direction
and state. Next, the desired count and memory address are programmed into DMA controller. The dmaEn
is set to 1, and the serviceIntr is set to “0”. To complete the process, the DMA channel with the DMA
controller is unmasked. The contents in the FIFO are emptied or filled by DMA using the right mode and
direction.
DMA is always transferred to or from the FIFO located at 0 x 400. By generating an interrupt and asserting
a serviceIntr, DMA is disabled when the DMA controller reaches the terminal count. By not asserting
LDRQ# for more than 32 consecutive DMA cycles, blocking of refresh requests is eliminated.
When it is necessary to disable a DMA while this is performing a data transfer, the host DMA controller is
disabled serviceIntr is then set to”1”, and dmaEn is next set to 0. The DMA will start again whether or not
the contents in FIFO are empty or full. This is done first by enabling the host DMA controller, then setting
dmaEn to “1”. The procedure is completed with serviceIntr set to 0. Upon the completion of a DMA transfer
in the forward direction, the software program must wait until the contents in FIFO are empty and the busy
line is low to ensure that all data reach the peripheral device successfully.
(17) Interrupts
When any of the following states are reached, it is necessary to generate an interrupt.
1. serviceIntr = 0, dmaEn = 0, direction = 0, and the number of PWords in the FIFO is greater than or equal
to writeIntrThreshold.
2. serviceIntr = 0, dmaEn = 0, direction = 1, and the number of PWords in the FIFO is greater than or equal
to readIntrThreshold.
3. serviceIntr = 0, dmaEn = 1, and DMA reaches the terminal count.
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相關(guān)代理商/技術(shù)參數(shù) |
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| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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