
IT8673F
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4. nErrIntrEn = 0 and nFault goes from high to low or when nErrIntrEn is set from “1” to “0” and nFault is
asserted.
5. ackIntEn = 1. In current implementations of using existing parallel ports, the generated interrupt may be
either edge trigger or level trigger type, making it "ISA-friendly".
(18) Interrupt Driven Programmed I/O
It is also possible to use an interrupt-driven programmed I/O to execute either ECP or parallel port FIFOs.
An interrupt will occur in the forward direction when serviceIntr is 0 and the number of free PWords in the
FIFO is equal to or greater than writeIntrThreshold. If either of these conditions is not met, it may be filled
with writeIntrThreshold PWords. An interrupt will occur in the reverse direction when serviceIntr is “0” and
the number of available PWords in the FIFO is equal to READIntrThreshold. If it is full, the FIFO can be
emptied completely in a single burst. If it is not full, only a number of PWords equal to READIntrThreshold
may be read from the FIFO in a single burst. In the Test mode, software can determine the values of
writeIntrThreshold, READIntrThreshold, and FIFO depth while accessing the FIFO.
Any PC ISA implementation that is adjusted to expedite DMA or I/O transfer must ensure that the
bandwidth on the ISA is maintained on the interface. Although the PC ISA bus cannot be directly controlled,
the interface bandwidth of the ECP port can be constrained to perform at the optimum speed.
(19) Standard Parallel Port
In the forward direction with DMA, the standard parallel port is run at or close to the permitted peak
bandwidth of 500 Kbytes/sec. The state machine does not examine nAck, but just begins the next DMA
based on the Busy signal.