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參數(shù)資料
| 型號(hào)： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級(jí)I / O）的初步規(guī)范V0.5 |
| 文件頁(yè)數(shù)： | 101/128頁(yè) |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
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(6) Device Status Register (dsr) (Primary Base+1h, Mode All)
Bits 0, 1 and 2 of this register are not implemented. These bit states remain at high in a read operation of
Printer Status Register.
dsr(7):This bit is the inverted level of the Busy input.
dsr(6): This bit is the state of the nAck input.
dsr(5): This bit is the state of the PError input.
dsr(4): This bit is the state of the Select input.
dsr(3): This bit is the state of the nFault input.
dsr(2)-dsr(0): These bits are always 1.
(7) Device Control Register (dcr) (Primary Base+2h, Mode All)
Bits 6 and 7 of this register supply no function. They are set high during the read operation, and cannot be
written. Contents in bits 0-5 are initialized to 0 when the RESET pin is active.
dcr(7)-dcr(6) : These two bits are always high.
dcr(5) : Except in modes 000 and 010, setting this bit low means that the PD bus is in output operation;
setting it high, in input operation. This bit will be forced low in mode 000.
dcr(4): Setting this bit high enables the interrupt request from the peripheral to the host due to a rising edge
of the nAck input.
dcr(3): It is inverted and output to the pin nSelectIn.
dcr(2): It is output to the pin nInit without inversion.
dcr(1): It is inverted and output to the pin nAutoFd.
dcr(0): It is inverted and output to the pin nStrobe.
(8) Parallel Port Data FIFO (cFifo) (Secondary Base+0h, Mode 010)
Bytes written or DMA transferred from the Host to this FIFO are sent by a hardware handshaking to the
peripheral according to the standard parallel port protocol. This operation is only defined for the forward
direction.
(9) ECP Data FIFO (ecpDFifo) (Secondary Base+0h, Mode 011)
When the direction bit dcr(5) is 0, bytes written or DMA transferred from the Host to this FIFO are sent by a
hardware handshaking to the peripheral according to the ECP parallel port protocol. When the dcr(5) is 1,
data bytes from the peripheral to this FIFO are read in an automatic hardware handshaking. The Host can
acquire these bytes by performing read operations or DMA transfers from this FIFO.
(10) Test FIFO Mode (tFifo) (Secondary Base+0h, Mode 110)
The Host may operate
read/write
or DMA transfers to this FIFO in any direction. Data in this FIFO will be
displayed on the PD bus without using hardware protocol handshaking. The tFifo will not accept new data
after it is full. Performing a read operation from an empty tFifo causes the last data byte to return.
(11) Configuration Register A (cnfgA) (Secondary Base+0h, Mode 111)
This
read only
register indicates to the system that interrupts are ISA-Pulses. This is an 8-bit
implementation by returning a 10h.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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