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參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 4/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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CONTENTS
Page
1. Features .......................................................................................................................................................1
2. General Description....................................................................................................................................2
3. Block Diagram.............................................................................................................................................3
4. Pinout Table.................................................................................................................................................4
5. Pin Configuration........................................................................................................................................5
6. IT8673F Pin Descriptions ...........................................................................................................................6
7. Special Pin Routings ................................................................................................................................11
8. List of GPIO Pins.......................................................................................................................................12
9. Power On Strapping Options...................................................................................................................13
10. Configuration.............................................................................................................................................14
10.1 Configuring Sequence Description .....................................................................................................14
10.2 Description of the Configuration Registers .........................................................................................16
10.2.1
Logical Device Base Address......................................................................................................20
10.3 Global Configuration Registers (LDN: All) ..........................................................................................21
10.3.1
Configure Control (Index=02h) ....................................................................................................21
10.3.2
Logical Device Number (LDN, Index=07h)..................................................................................21
10.3.3
Chip ID Byte 1 (Index=20h, Default=86h)....................................................................................21
10.3.4
Chip ID Byte 2 (Index=21h, Default=73h)....................................................................................21
10.3.5
Chip Version (Index=22h, Default=01h) ......................................................................................21
10.3.6
Clock Selection Register (Index=23h, Default=00h)....................................................................21
10.3.7
Software Suspend (Index=24h, Default=00h, MB PnP)..............................................................21
10.3.8
GPIO Multi-Function Pin Selection Register (Index=25h, Default=00h)......................................22
10.3.9
Reserved Register (Index=26h, Default=00h).............................................................................22
10.3.10 Reserved Register (Index=27h, Default=00h).............................................................................22
10.3.11 Reserved Register (Index=28h, Default=00h).............................................................................22
10.3.12 Reserved Register (Index=29h, Default=00h).............................................................................22
10.3.13 Test 1 Register (Index=2Eh, Default=00h)..................................................................................22
10.3.14 Test 2 Register (Index=2Fh, Default=00h) ..................................................................................22
10.4 FDC Configuration Registers (LDN=00h)...........................................................................................22
10.4.1
FDC Activate (Index=30h, Default=00h)......................................................................................22
10.4.2
FDC Base Address MSB Register (Index=60h, Default=03h).....................................................23
10.4.3
FDC Base Address LSB Register (Index=61h, Default=F0h) .....................................................23
10.4.4
FDC Interrupt Level Select (Index=70h, Default=06h) ................................................................23
10.4.5
FDC DMA Channel Select (Index=74h, Default=02h).................................................................23
10.4.6
FDC Special Configuration Register (Index=F0h, Default=00h) .................................................23
10.5 Serial Port 1 Configuration Registers (LDN=01h)...............................................................................23
10.5.1
Serial Port 1 Activate (Index=30h, Default=00h).........................................................................23
10.5.2
Serial Port 1 Base Address MSB Register (Index=60h, Default=03h)..........................................24
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