
IT8673F
(2)
2
MODEM Status Register (MSR) (Read/Write, Address offset=6)
This 8-bit register indicates the current state of the control lines with modems or peripheral devices in
addition to this current state information. Four of these eight bits MSR(4) - MSR(7) can provide the state
change information when a modem control input changes state. It is reset low when the Host reads the
MSR.
Table 11-35. Modem Status Register Descriptiopn
Bit
Default
Description
7
0
Data Carrier Detect
Data Carrier Detect - Indicates the complement status of Data Carrier Detect
(DCD#) input. If MCR(4) = 1, MSR(7) is equivalent to OUT2 of the MCR.
Ring Indicator
Ring Indicator (RI#) - Indicates the complement status to the RI# input. If
MCR(4)=1, MSR(6) is equivalent to OUT1 in the MCR.
Data Set Ready
Data Set Ready (DSR#) - Indicates that the modem is ready to provide
received data to the serial channel receiver circuitry. If the serial channel is in
the loop mode (MCR(4) = 1), MSR(5) is equivalent to DTR# in the MCR.
Clear to Send
Clear to Send (CTS#) - Indicates the complement of CTS# input. When the
serial channel is in the loop mode (MCR(4)=1), MSR(5) is equivalent to RTS#
in the MCR.
Delta Data Carrier Detect
Indicates that the DCD# input state has been changed since the last time read
by the Host.
Trailing Edge Ring Indicator
Indicates that the RI input state to the serial channel has been changed from a
low to high since the last time read by the Host. The change to logic 1 does not
activate the TERI.
Delta Data Set Ready
Delta Data Set Ready (DDSR) - A logic "1" indicates that the DSR# input state
to the serial channel has been changed since the last time read by the Host.
Delta Clear to Send
This bit indicates the CTS# input to the chip has changed state since the last
time the MSR was read.
6
0
5
0
4
0
3
0
2
0
1
0
0
0