參數(shù)資料
型號： IT8673F
廠商： Electronic Theatre Controls, Inc.
英文描述： GT 35C 35#12 SKT PLUG
中文描述： 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5
文件頁數(shù)： 93/128頁
文件大小： 780K
代理商： IT8673F
IT8673F
11.5.4 Reset
The reset of the IT8673F should be held to an idle mode reset high for 500 ns until initialization, and this
causes the initialization of the transmitter and receiver internal clock counters.
3
Table 11-36. Reset Control of Registers and Pinout Signals
Register/Signal
Reset Control
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset Status
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT1, SOUT2
RTS0#, RTS1#, DTR0#, DTR1#
IRQ of Serial Port
All bits Low
Bit 0 is high and bits 1-7 are low
All bits Low
All bits Low
All bits Low
Bits 5 and 6 are high, others are low
Bits 0-3 low, bits 4-7 input signals
High
High
High Impedance
11.5.5 Programming
Each serial channel of the IT8673F is programmed by control registers, whose contents define the
character length, number of stop bits, parity, baud rate and modem interface. Even though the control
register can be written in any given order, the IER should be the last register written because it controls the
interrupt enables. After the port has been programmed, these registers can still be updated whenever the
port is not transferring data.
11.5.6 Software Reset
This approach allows the serial port returning to a completely known state without a system reset. This is
achieved by writing the required data to the LCR, DLL, DLM and MCR. The LSR and RBR must be read
before enabling interrupts to clear out any residual data or status bits that may be invalid for subsequent
operations.
11.5.7 Clock Input Operation
The input frequency of the Serial Channel is 24 MHz
÷
13, not exactly 1.8432 MHz.
11.5.8 FIFO Interrupt Mode Operation
(1) RCVR Interrupt
When setting FCR(0)=1 and IER(0)=1, the RCVR FIFO and receiver interrupts are enabled. The RCVR
interrupt occurs under the following conditions:
a. The receive data available interrupt and the IIR, receive data available indication, will be issued only if the
FIFO has reached its programmed trigger level. They will be cleared as soon as the FIFO drops below its
trigger level
b. The receiver line status interrupt has higher priority over the received data available interrupt
c. The time-out timer will be reset after receiving a new character or after the Host reads the RCVR FIFO
whenever a time-out interrupt occurs. The timer will be reset when the Host reads one character from the
RCVR FIFO
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IT8687R 制造商:ITE 功能描述:
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IT86C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220
IT86F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220
IT86G 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220
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