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參數(shù)資料
| 型號(hào)： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級(jí)I / O）的初步規(guī)范V0.5 |
| 文件頁(yè)數(shù)： | 117/128頁(yè) |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
107
11.8.6.9 CIR Receiver FIFO Status Register (RSR)
The RSR, an 8-bit
read only
register, provides the Receiver FIFO status.
Address: Base address + 6h
Bit
R/W
Default
Description
7
R
0b
Receiver FIFO Time-out (RXFTO)
This bit will be set to “1” when a Receiver FIFO time-out condition occurs.
The conditions that must exist for a Receiver FIFO time-out condition to occur
include the followings:
a. At least one byte has been in the Receiver FIFO is not empty for 64 ms or
more, and
b. The receiver has been inactive (RXACT=0) for over 64 ms or more, and
c. More than 64 ms have elapsed since the last byte was read from the
Receiver FIFO by the CPU
Reserved
6
-
-
5 – 0
R
000000b
Receiver FIFO Byte Count (RXFBC)
Return the number of bytes left in the Receiver FIFO.
11.8.6.10
The IIR, an 8-bit
read only
register, is used to identify the pending interrupts.
CIR Interrupt Identification Register (IIR)
Address: Base address + 7h
Bit
R/W
Default
Description
7 - 3
-
-
Reserved
2 – 1
R
00b
Interrupt Identification
These two bits are used to identify the source of the pending interrupts.
IID[1:0] Interrupt Source
00 No interrupt
01 Transmitter Low Data Level Interrupt
10 Receiver Data Stored Interrupt
11 Receiver FIFO Overrun Interrupt
Interrupt Pending
This bit will be set to “1” while an interrupt is pending.
0
R
1b
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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