- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383185 > IT8673F (Electronic Theatre Controls, Inc.) GT 35C 35#12 SKT PLUG PDF資料下載
參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 96/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁當前第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
IT8673F
11.6.1 SPP and EPP Modes
6
Table 11-38. Address Map and Bit Map for SPP and EPP Modes
Register
Address
I/O
D0
D1
D2
D3
D4
D5
D6
D7
Mode
Data Port
Base+0h
R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SPP/EPP
Status Port
Base+1h
R
TMOUT
1
1
ERR# SLCT
PE
ACK# BUSY# SPP/EPP
Control Port
Base+2h
R/W
STB
AFD
INIT
SLIN
IRQE PDDIR
1
1
SPP/EPP
EPP Address Port
Base+3h
R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
EPP Data Port0
Base+5h
R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
EPP Data Port1
Base+5h
R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
EPP Data Port2
Base+6h
R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
EPP Data Port3
Base+7h
R/W
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
EPP
Note
1. The Base Address depends on the Logical Device configuration registers of Parallel Port (0X60, 0X61).
(1) Data Port (Primary Base Address + 00h)
This is a bi-directional 8-bit data port. The direction of data flow is determined by the bit 5 of the logic state
of the control port register. It forwards directions when the bit is low and reverses directions when the bit is
high.
(2) Status Port (Primary Base Address + 01h)
This is a
read only
register. Writing to this register has no effects. The contents of this register are latched
during an IOR cycle.
Bit 7 - BUSY#: Inverse of printer BUSY signal, a logic "0" means that the printer is busy and cannot accept
another character. A logic "1" means that it is ready to accept the next character.
Bit 6 - ACK#: Printer acknowledge, a logic "0" means that the printer has received a character and is ready
to accept another. A logic "1" means that it is still processing the last character.
Bit 5 - PE: Paper end, a logic "1" indicates the paper end.
Bit 4 - SLCT: Printer selected, a logic "1" means that the printer is on line.
Bit 3 - ERR#: Printer error signal, a logic "0" means an error has been detected.
Bits 1, 2: Reserved, these bits are always "1" when read.
Bit 0 - TMOUT: This bit is valid only in EPP mode and indicates that a 10-msec time-out has occurred in
EPP operation. A logic "0" means no time-out occurred and a logic “1” means that a time-out error has been
detected. This bit is cleared by a RESET or by writing a logic “1” to it. When the IT8673F are selected to
non-EPP mode (SPP or ECP), this bit is always logic "1" when read.
(3) Control Port (Primary Base Address +02h)
This port provides all output signals to control the printer. The register can be read and written.
Bits 7, 6 : Reserved, these two bits are always "1" when read.
Bit 5 PDDIR: Data port direction control, this bit determines the direction of the data port. Set this bit "0" to
output the data port to PD bus and "1" to input from PD bus.
Bit 4 IRQE: Interrupt request enable, setting this bit "1" enables the interrupt requests from the parallel port
to the Host. An interrupt request is generated by a "0" to "1" transition of the ACK# signal.
Bit 3 SLIN: Inverse of SLIN# pin, setting this bit to "1" selects the printer.
Bit 2 INIT: Initiate printer, setting this bit to "0" initializes the printer.
Bit 1 AFD: Inverse of the AFD# pin, setting this bit to "1" causes the printer to automatically feed after each
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IT8687R | GT 35C 35#12 SKT PLUG |
| ITC1000 | GT 85C 85#16 SKT PLUG |
| ITF86130SK8T | N-Channel, Logic Level, Power MOSFET(N溝道邏輯電平功率MOS場效應(yīng)管) |
| ITF86182SK8T | 11A, 30V, 0.0115 Ohm, P-Channel, Logic Level, Power MOSFET |
| ITF87012SVT | 6A, 20V, 0.035 Ohm, N-Channel,2.5V Specified Power MOSFET(6A, 20V, 0.035Ω N溝道2.5V專用功率MOS場效應(yīng)管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。