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| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 100/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
(3) ECP Pin Descriptions
0
Table 11-42. ECP Pin Descriptions
Name
Type
Description
nStrobe (HostClk)
O
Used for handshaking with Busy to write data and addresses into the peripheral
device.
PD0-PD7
I/O
Address or data or RLE data.
nAck (PeriphClk)
I
Used for handshaking with nAutoFd to transfer data from the peripheral device to
the Host.
Busy (PeriphACK)
I
The peripheral uses this signal for flow control in the forward direction
(hand-shaking with nStrobe). In the reverse direction, this signal is used to
determine whether a command or data information is present on PD0-PD7.
PError
(nAckReverse)
I
Used to acknowledge nInit from the peripheral which drives this signal low, allowing
the host to drive the PD bus.
Select
I
Printer On-Line indication.
nAutoFd (HostAck)
O
In the reverse direction, it is used for handshaking between the nAck and the Host.
When it is asserted, a peripheral data byte is requested. In the forward direction,
this signal is used to determine whether a command or data information is present
on PD0-PD7.
nFault
(nPeriphRequest)
I
In the forward direction (only), the peripheral is allowed (but not required) to assert
this signal (low) to request a reverse transfer while in ECP mode. The signal
provides a mechanism for peer-to-peer communication. It is typically used to
generate an interrupt to the host, which has the ultimate control over the transfer
direction.
nInit
(nReverseRequest)
O
The host may drive this signal low to place the PD bus in the reverse direction. In
the ECP mode, the peripheral is permitted to drive the PD bus when nInit is low and
nSelectIn is high.
nSelectIn (1284
Active)
O
Always inactive (high) in the ECP mode.
(4) Data Port (Primary Base+0h, Modes 000 and 001)
Its contents will be cleared by a RESET. In a write operation, the contents of the data bus are latched by
Data Register at the rising edge of the IOW# input. The contents are then sent without being inverted to
PD0-PD7. The contents of data ports are read and sent to the host in a read operation.
(5) ecpAFifo PORT (Address/RLE) (Primary Base+0h, Mode 011)
Any data byte written to this port are placed in the FIFO and tagged as an ECP Address/RLE. The hardware
then sends this data automatically to the peripheral. The operation of this port is only valid in forward
direction (dcr(5)=0).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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