- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383185 > IT8673F (Electronic Theatre Controls, Inc.) GT 35C 35#12 SKT PLUG PDF資料下載
參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 58/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當(dāng)前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
IT8673F
11.4.3 Hardware Reset (RESET Pin)
When the FDC receives a RESET signal, all registers of the FDC core are cleared (except those
programmed by the SPECIFY command). To exit the reset state, the host must clear the DOR bit.
8
48
11.4.4 Software Reset (DOR Reset and DSR Reset)
When the reset bit in the DOR or the DSR is set, all registers of the FDC core are cleared. A reset
performed by setting the reset bit in the DOR has higher priority over a reset performed by setting the reset
bit in the DSR. In addition, to exit the reset state, the DSR bit is self-clearing, while the host must clear the
DOR bit.
11.4.5 Digital Data Separator
The internal digital data separator is comprised of a digital PLL and associated support circuitry. It is
responsible for synchronizing the raw data signal read from the floppy disk drive. The synchronized signal is
used to separate the encoded clock from the data pulses.
11.4.6 Write Precompensation
Write precompensation is a method that can be used to adjust the effects of bit shift on data as it is written
to the disk. It is harder for the data separator to read data that has been subject to bit shifting. Soft read
errors can occur due to such bit shifting. Write precompensation predicts where the bit shifting might occur
within a data pattern and shifts the individual data bits back to their nominal positions. The FDC permits the
selection of write precompensation via the Data Rate Select Register (DSR) bits 2 through 4.
11.4.7 Data Rate Selection
Selecting one of the four possible data rates for the attached floppy disks is accomplished by setting the
Diskette Control Register (DCR) or Data Rate Select Register (DSR) bits to 0 and 1. The data rate is
determined by the last value that is written to either the DCR or the DSR. When the data rate is set, the data
separator clock is scaled appropriately.
11.4.8 Status, Data and Control Registers
11.4.8.1 Digital Output Register (DOR, FDC Base Address + 02h)
This is a Read/Write register. It controls drive selection and motor enables as well as a software reset bit
and DMA enable. The I/O interface reset may be used at any time to clear the DOR’s contents.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IT8687R | GT 35C 35#12 SKT PLUG |
| ITC1000 | GT 85C 85#16 SKT PLUG |
| ITF86130SK8T | N-Channel, Logic Level, Power MOSFET(N溝道邏輯電平功率MOS場效應(yīng)管) |
| ITF86182SK8T | 11A, 30V, 0.0115 Ohm, P-Channel, Logic Level, Power MOSFET |
| ITF87012SVT | 6A, 20V, 0.035 Ohm, N-Channel,2.5V Specified Power MOSFET(6A, 20V, 0.035Ω N溝道2.5V專用功率MOS場效應(yīng)管) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。