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參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 110/128頁 |
| 文件大小： | 780K |
| 代理商： | IT8673F |
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IT8673F
100
11.8.6.1 CIR Data Register (DR)
The DR, an 8-bit
read/write
register, is the data port for CIR. Data are transmitted and received through this
register.
Address: Base address + 0h
Bit
R/W
Default
Description
7 – 0
R/W
FFh
CIR Data Register (DR[7:0])
Writing data to this register causes data to be written to the Transmitter FIFO.
Reading data from this register causes data to be received from the Receiver
FIFO.
11.8.6.2 CIR Interrupt Enable Register (IER)
The IER, an 8-bit
read/write
register, is used to enable the CIR interrupt request.
Address: Base address + 1h
Bit
R/W
Default
Description
7 – 6
-
-
Reserved for ITE use.
5
R/W
0b
RESET (RESET)
This bit is a software reset function. Writing a “1” to this bit resets the registers
of DR, IER, TCR1, BDLR, BDHR and IIR. This bit is then cleared to initial
value automatically.
4
R/W
0b
Baud Rate Register Enable Function Control (BR)
This bit is used to control the baud rate registers enable read/write function.
Set this bit to “1” to enable the baud rate registers for CIR.
Set this bit to “0” to disabdle the baud rate registers for CIR.
3
R/W
0b
Interrupt Enable Function Control (IEC)
This bit is used to control the interrupt enable function.
Set this bit to “1” to enable the interrupt request for CIR.
Set this bit to “0” to disable the interrupt request for CIR.
2
R/W
0b
Receiver FIFO Overrun Interrupt Enable (RFOIE)
This bit is used to control Receiver FIFO Overrun Interrupt request.
Set this bit to “1” to enable Receiver FIFO Overrun Interrupt request.
Set this bit to “0” to disable Receiver FIFO Overrun Interrupt request.
Receiver Data Available Interrupt Enable (RDAIE)
This bit is used to enable Receiver Data Available Interrupt request. The
Receiver will generate this interrupt when the data available in the FIFO
exceed the FIFO Threshold Level.
Set this bit to “1” to enable Receiver Data Available Interrupt request.
Set this bit to “0” to disable Receiver Data Available Interrupt request.
Transmitter Low Data Level Interrupt Enable (TLDLIE)
This bit is used to enable Transmitter Low Data Level Interrupt request. The
Transmitter will generate this interrupt when the data available in the FIFO are
less than the FIFO threshold Level.
Set this bit to “1” to enable Transmitter Low Data Level Interrupt request.
Set this bit to “0” to disable Transmitter Low Data Level Interrupt request.
1
R/W
0b
0
R/W
0b
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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