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| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 91/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
11.5.3 Status Registers: LSR and MSR
(1)
Line Status Register (LSR) (Read/Write, Address offset=5)
This register provides status indications and is usually the first register read by the CPU to determine the
cause of an interrupt or to poll the status of each serial channel. The contents of the LSR are described
below:
1
Table 11-34. Line Status Register Description
Bit
Default
Description
7
0
Error in Receiver FIFO
In 16450 mode, this bit is always 0. In the FIFO mode, it sets high when there
is at least one parity error, framing or break interrupt in the FIFO. This bit is
cleared when the CPU reads the LSR, if there are no subsequent errors in the
FIFO.
Transmitter Empty
This
read only
bit indicates that the Transmitter Holding Register and
Transmitter Shift Register are both empty. Otherwise, this bit is "0," and has
the same function in the FIFO mode.
Transmitter Holding Register Empty
Transmitter Holding Register Empty (THRE). This
read only
bit indicates that
the TBR is empty and is ready to accept a new character for transmission. It is
set high when a character is transferred from the THR into the Transmitter
Shift Register, causing a priority 3 IIR interrupt which is cleared by a read of
IIR. In the FIFO mode, it is set when the XMIT FIFO is empty and is cleared
when at least one byte is written to the XMIT FIFO.
Line Break
Break Interrupt (BI) status bit indicates that the last character received was a
break character, (invalid but entire character), including parity and stop bits.
This occurs when the received data input is held in the spacing (logic 0) for
longer than a full word transmission time (start bit + data bits + parity + stop
bit). When any of these error conditions is detected (LSR(1) to LSR(4)), a
Receiver Line Status interrupt (priority 1) will be generated in the IIR with the
IER(2) enabled previously.
Framing Error
Framing Error (FE) bit, a logic 1, indicates that the stop bit in the received
character was not valid. It resets low when the CPU reads the contents of the
LSR.
Parity Error
The parity error (PE) indicates by with a logic 1 that the received data
character does not have the correct even or odd parity, as selected by LCR(4).
It will be reset to "0" whenever the LSR is read by the CPU.
Overrun Error
Overrun Error (OE) bit indicates by a logic 1 that the RBR has been
overwritten by the next character before it had been read by the CPU. In the
FIFO mode, the OE occurs when the FIFO is full and the next character has
been completely received by the Shift Register. It will be reset when the LSR is
read by the CPU.
Data Ready
A "1" indicates a character has been received by the RBR. And a logic "0"
indicates all the data in the RBR or the RCVR FIFO have been read.
6
1
5
1
4
0
3
0
2
0
1
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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