
46
Functional Operation
Chapter 3
AMD-8111 HyperTransport I/O Hub Data Sheet
24674
Rev. 3.00
April 2003
AMD Preliminary Information
3.4.3
Watchdog Timer (WDT)
The watchdog timer is a down counter starting at a programmed value. It resets or shuts down the
system if the count reaches zero. Operating system services periodically restart the timer so that if the
operating system, drivers or services stop functioning, the system is automatically restarted or shut
down.
The watchdog timer is enabled or disabled by programming DevB:0xA8. When disabled, the
watchdog timer stops counting and cannot be started by the operating system. When enabled, the
watchdog timer supports two sub-states, the Running and the Stopped states. The watchdog timer
allows the operating system to set it in either Running or Stopped state by programming
WDT00[RSTOP]. In the Enabled/Stopped state the timer does not count down. In the
Enabled/Running state the counter counts down to zero once triggered. These states are visible to the
operating system through WDT00[WDE_ALIAS] and WDT00[RSTOP].
When DevB:0xA8[WDTSILENT] is set, the watchdog timer operates in silent mode. In that mode no
action, as defined in WDT00[WACT], is caused when the timer expires. It is in the responsibility of
external software to cause either a power down/power up or a system reset and to clear
WDT00[WFIR] directly.
The status of WDT00[WFIR] can be observed externally on GPIO4 when the GPIO is programmed
for its alternate function through PMC4.
The count down time range can be programmed by writing WDT08.
3.4.4
High Precision Event T
imer
(HPET)
3.4.4.1
Overview
The HPET consists of a block of three timers. This block contains a 32-bit up counter with three 32-
bit output comparators each for one timer. Timer 0 can operate in either periodic or non-periodic
mode, timer 1 and 2 only in non-periodic mode.
Table 17.
HPET Specifications
Item
Implementation
Main Counter
Clock Frequency
Number of comparators
Number of Periodic Capable Timer
Number of One-Shot Capable Timer
Interrupt Routing
32-bit up-counter
14.31818 MHz
3 32-bit comparators
1 Timer 0
3 Timer 0, 1, 2
Through PIC, IOAPIC and HyperTransport link