
Chapter 4
Registers
259
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
AC
‘
97 Audio Controller Current Index Value
AC04, AC14, AC24
Default:
00h
Attribute:
See below.
AC
‘
97 Audio Controller Last Valid Index
AC05, AC15, AC25
Default:
00h
Attribute:
See below.
AC
‘
97 Audio Controller Status
AC06, AC16, AC26
Default:
0001h
Attribute:
See below.
Bits
7:5
4:0
Description
0h
CIV. Current Index Value
. Read-only. These bits represent which buffer descriptor within the list of 32
descriptors is being processed currently. As each descriptor is processed, this value is incremented.
Bits
7:5
4:0
Description
0h
LVI.
Read-write. These bits indicate the last valid descriptor in the list. This value is updated by the
software as it prepares new buffers and adds to the list.
Bits
15:5
4
Description
Reserved.
FIFOERR. FIFO Error
. Read-write. The hardware sets this bit if an under-run or over-run occurs. This
bit is cleared by writing a 1 to this bit position.
BCIS. Buffer Completion Interrupt Status
. Read-write. This bit is set by the hardware after the last
sample of a buffer has been processed, and if the Interrupt on Completion (IOC) bit is set in the
command byte of the buffer descriptor. Remains active until software clears bit. This bit is cleared by
writing a 1 to this bit position.
LVBCI. Last Valid Buffer Completion Interrupt
. Read-write.This bit is set to 1 by hardware when last
valid buffer has been processed. It remains active until cleared by software. This bit indicates the
occurrence of the event signi
fi
ed by the last valid buffer being processed. Thus, this is an event status
bit that can be cleared by software once this event has been recognized. This event causes an
interrupt if the enable bit in the Control Register is set. This bit is cleared by writing a
“
1
”
to this bit
position.
CELV. Current Equals Last Valid
. Read-only.1 = Current Index is equal to the value in the Last Valid
Index Register, and the buffer pointed to by the CIV has been processed (i.e., after the last valid buffer
has been processed). This bit is very similar to bit 2, except this bit re
fl
ects the state rather than the
event. This bit re
fl
ects the state of the controller, and remains set until the controller exits this state.
Hardware clears this bit when controller exits state (i.e., until a new value is written to the LVI register).
BMCH. Bus master controller halted
. Read-only. This bit is set to 1b because of the Run/Pause bit
being cleared in which case BMCH may or may not be asserted immediately, depending on whether a
PCI transaction had previously been requested. If a PCI transaction had previously been requested,
BMCH assertion occurs after completion of the single transaction. Bus master controller halted can
also happen once the controller has processed the last valid buffer in which case it sets ACx6[CELV]
and halts. This bit is cleared and the bus master controller resumes operation when both the Run/
Pause bit is set and the controller has exited the ACx6[CELV] status.
3
2
1
0