
Chapter 4
Registers
301
24674
Rev. 3.00
April 2003
AMD-8111 HyperTransport I/O Hub Data Sheet
AMD Preliminary Information
7
SUSP. Suspend
.
Read-write. 1= Port in suspend state. 0= Port not in suspend state. Port Enabled Bit and Suspend bit
of this register de
fi
ne the port states as follows:
Bits [Port Enabled, Suspend]Port State
0X
Disable
10
Enable
11
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port reset.
The blocking occurs at the end of the current transaction, if a transaction was in progress when this
bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit
status does not change until the port is suspended and that there may be a delay in suspending a
port if there is a transaction currently in progress on the USB.
A write of zero to this bit is ignored by the host controller. The host controller unconditionally sets this
bit to a zero when:
Software sets the Force Port Resume bit to a zero (from a one).
Software sets the Port Reset bit to a one (from a zero).
If host software sets this bit to a one when the port is not enabled (i.e., Port enabled bit is a zero) the
results are unde
fi
ned.
This bit resides in the AUX power domain.
FPR. Force Port Resume
.
Read-write. 1= Resume detected/driven on port. 0= No resume (K-state) detected/driven on port.
This functionality de
fi
ned for manipulating this bit depends on the value of the Suspend bit. For
example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions
this bit to a one, then the effects on the bus are unde
fi
ned.
Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-
K transition is detected while the port is in the Suspend state. When this bit transitions to a one
because a J-to-K transition is detected, the Port Change Detect bit in the ECAP34 register is also set
to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume sequence follows the de
fi
ned
sequence documented in the USB Speci
fi
cation Revision 2.0. The resume signaling (Full-speed
‘
K
’
)
is driven on the port as long as this bit remains a one. Software must appropriately time the Resume
and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one)
causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle).
This bit remains a one until the port has switched to the high-speed idle. The host controller must
complete this transition within 2 milliseconds of software setting this bit to a zero.
This bit resides in the AUX power domain.
OCC. Over-current Change
.
Read; write 1 to clear. This bit gets set to a one when there is a change to Over-current Active.
This bit resides in the AUX power domain.
OCA. Over-current Active
.
Read-only. 1= This port currently has an over-current condition. 0= This port does not have an over-
current condition. This bit automatically transitions from a one to a zero when the over current
condition is removed.
6
5
4
Bits
Description