
232
Registers
Chapter 4
AMD-8111 HyperTransport I/O Hub Data Sheet
24674
Rev. 3.00
April 2003
AMD Preliminary Information
TCO Status 2 Register
PM46
Default:
00h.
Attribute:
Read; set by hardware; write 1 to clear.
TCO Control 1 Register
PM48
Default:
0000h.
Attribute:
Read-write.
TCO Control 2 Register
PM4A
Default:
00h.
Attribute:
Read-write.
Bits
7:4
3
Description
Reserved.
TT_STS. THERMTRIP status.
1=THERMTRIP_L was asserted while PWRON_L = 0, PWROK = 1,
and RESET_L = 1. This bit resides in the VDD_COREX power plane.
BOOT_STS. Boot status.
1=Hardware sets this bit when PM46[2NDTO_STS] changes from 0 to 1
after any RESET_L before any ROM accesses have occurred. This bit resides on the VDD_COREX
power plane.
2NDTO_STS. Second TCO time out status.
1=Hardware sets this bit when the TCO timer, PM40,
times out a second time before PM44[TOUT_STS] is cleared. If enabled by
DevB:3x48[NO_REBOOT], this may trigger a reboot of the system. This bit resides on the
VDD_COREX power plane.
INTRDR_STS. Intruder detect status.
1=Hardware sets this bit when the INTRUDER_L pin is
asserted for more than 60 microseconds (debounce time); this bit functions in all power states (unless
AL is not powered). This bit resides in the VDD_COREAL power plane; when VDD_COREAL is
powered, this bit defaults to 0. This may trigger an interrupt as speci
fi
ed by PM4A[INTRDR_SEL].
2
1
0
Bits
15:12 Reserved.
11
TCOHALT. TCO timer halt.
1=Freeze the TCO timer (PM40) in its current state; PM44[TOUT_STS]
and PM46[2NDTO_STS] cannot be set.
10
Reserved.
9
NMI2SMI_EN. NMI interrupts generate SMI interrupts.
1=Whenever an NMI is detected,
PM44[NMI2SMI_STS] is set and no NMI is generated; this bit does not affect NMI_NOW (setting
NMI_NOW generates an NMI regardless of the state of NMI2SMI_EN). Note: if this bit is set and
RTC70[NMIDIS] is set, then no NMIs or associated SMIs are generated.
8
NMI_NOW. Generate NMI.
1=Generate NMI. It is expected that the NMI handler clears this bit.
7:0
Reserved.
Description
Bits
7:3
2:1
Description
Reserved.
INTRDR_SEL.
Select the action to take if PM46[INTRDR_STS] is set. 00b=Reserved; 01b=IRQ (as
speci
fi
ed by DevB:3x44[TCO_INT_SEL]); 10b=SMI; 11b=Reserved.
Reserved.
0