參數(shù)資料
型號: LXP710PE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 29/84頁
文件大?。?/td> 1108K
代理商: LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
LXP710
Datasheet
29
HDSL Loop 1 Time Slot Control Byte (12 bytes)
Address: 07
Abbreviation: L1TSCTL1
Read/Write
Address: 08
Abbreviation: L1TSCTL2
Read/Write
2
SWAPEN
0
Preferred Loop Enable. When High, time slot tables of Loop 1 and Loop 2 are swapped.
1
LDTABLE
0
Load Time Slot Grouping Table. When High, time slot grouping tables are loaded into
Mux and Demux blocks and the bit is cleared automatically.
0
FULLE1
0
Full E1/Fractional E1 Control. When High, fractional E1 application is selected. When
Low, full E1 is selected.
Table 9. Time Slot Grouping Table Control Register (Continued)
Bit
Name
Default
Description
Table 10. Loop 1 Time Slot Control Byte 1
Bit
Name
Default
Description
7
TSG0
1
Loop 1 Time Slot Grouping (Byte 1). Each bit that is set Low blocks transmission of
the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
6
TSG1
1
5
TSG2
0
4
TSG3
1
3
TSG4
0
2
TSG5
1
1
TSG6
0
0
TSG7
1
Table 11. Loop 1 Time Slot Control Byte 2
Bit
Name
Default
Description
7
TSG8
0
Loop 1 Time Slot Grouping (Byte 2). Each bit that is set Low blocks transmission of
the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
6
TSG9
1
5
TSG10
0
4
TSG11
1
3
TSG12
0
2
TSG13
1
1
TSG14
0
0
TSG15
1
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