
R8C/3GM Group
11. Interrupts
R01UH0284EJ0100 Rev.1.00
Aug 09, 2011
11.6
Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When the
on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1,
and fixed vector tables) in the user system.
Set the starting address of any instruction in the RMADi register (i = 0 or 1). The AIERi0 bit in the AIERi register
can be used to select enable or disable the interrupt. The address match interrupt is not affected by the I flag and
IPL.
request is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The
appropriate return address is not saved on the stack.) When returning from the address match interrupt, follow one
of the following means:
Rewrite the contents of the stack and use the REIT instruction to return.
Use an instruction such as POP to restore the stack to its previous state before the interrupt request was
acknowledged. Then use a jump instruction to return.
Notes:
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles
contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 11.8
PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1)
Instruction with 2-byte operation code
(2) Instruction with 1-byte operation code
(2)ADD.B:S
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S
#IMM8,dest
OR.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZ
#IMM8,dest
STNZ
#IMM8,dest
STZX
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
POPM
dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (however, dest = A0 or A1)
Address indicated by
RMADi register + 2
Instructions other than above
Address indicated by
RMADi register + 1
Table 11.9
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0
AIER00
RMAD0
Address match interrupt 1
AIER10
RMAD1